SLAZ095Z October 2012 – May 2021 CC430F5143
USCI Module
Functional
Violation of setup and hold times for (repeated) start in I2C master mode
In I2C master mode, the setup and hold times for a (repeated) START, tSU,STA and tHD,STA respectively, can be violated if SCL clock frequency is greater than 50kHz in standard mode (100kbps). As a result, a slave can receive incorrect data or the I2C bus can be stalled due to clock stretching by the slave.
If using repeated start, ensure SCL clock frequencies is < 50kHz in I2C standard mode (100 kbps).