米6体育平台手机版

SLAZ098AA October 2012 – May 2021 CC430F6125

1Functional Advisories
2Preprogrammed Software Advisories
3Debug Only Advisories
4Fixed by Compiler Advisories
5Nomenclature, Package Symbolization, and Revision Identification
6Advisory Descriptions
1. 6.1 AES1
2. 6.2 BSL7
3. 6.3 COMP4
4. 6.4 COMP10
5. 6.5 CPU18
6. 6.6 CPU20
7. 6.7 CPU21
8. 6.8 CPU22
9. 6.9 CPU23
10. 6.10 CPU24
11. 6.11 CPU25
12. 6.12 CPU26
13. 6.13 CPU27
14. 6.14 CPU28
15. 6.15 CPU29
16. 6.16 CPU30
17. 6.17 CPU31
18. 6.18 CPU32
19. 6.19 CPU33
20. 6.20 CPU34
21. 6.21 CPU35
22. 6.22 CPU39
23. 6.23 CPU40
24. 6.24 CPU46
25. 6.25 CPU47
26. 6.26 DMA4
27. 6.27 DMA7
28. 6.28 DMA8
29. 6.29 DMA10
30. 6.30 EEM8
31. 6.31 EEM9
32. 6.32 EEM11
33. 6.33 EEM13
34. 6.34 EEM14
35. 6.35 EEM16
36. 6.36 EEM17
37. 6.37 EEM19
38. 6.38 EEM23
39. 6.39 FLASH29
40. 6.40 FLASH31
41. 6.41 FLASH37
42. 6.42 JTAG20
43. 6.43 JTAG26
44. 6.44 JTAG27
45. 6.45 LCDB1
46. 6.46 LCDB3
47. 6.47 LCDB4
48. 6.48 LCDB5
49. 6.49 LCDB6
50. 6.50 MPY1
51. 6.51 PMAP1
52. 6.52 PMM8
53. 6.53 PMM9
54. 6.54 PMM10
55. 6.55 PMM11
56. 6.56 PMM12
57. 6.57 PMM14
58. 6.58 PMM15
59. 6.59 PMM17
60. 6.60 PMM18
61. 6.61 PMM20
62. 6.62 PORT15
63. 6.63 PORT16
64. 6.64 PORT17
65. 6.65 PORT19
66. 6.66 PORT21
67. 6.67 RF1A1
68. 6.68 RF1A2
69. 6.69 RF1A3
70. 6.70 RF1A5
71. 6.71 RF1A6
72. 6.72 RF1A8
73. 6.73 RTC3
74. 6.74 RTC6
75. 6.75 SYS16
76. 6.76 TAB23
77. 6.77 UCS6
78. 6.78 UCS7
79. 6.79 UCS9
80. 6.80 UCS10
81. 6.81 UCS11
82. 6.82 USCI26
83. 6.83 USCI30
84. 6.84 USCI31
85. 6.85 USCI34
86. 6.86 USCI35
87. 6.87 USCI39
88. 6.88 USCI40
89. 6.89 WDG4
7Revision History

6.61 PMM20

PMM Module

Function

Unexpected SVSL/SVML event during wakeup from LPM2/3/4 in fast wakeup mode

Description

If PMM low side is configured to operate in fast wakeup mode, during wakeup from LPM2/3/4 the internal VCORE voltage can experience voltage drop below the corresponding SVSL and SVML threshold (recommendation according to User's Guide) leading to an unexpected SVSL/SVML event. Depending on PMM configuration, this event triggers a POR or an interrupt.

Note: As soon the SVSL or the SVML is enabled in Normal performance mode the device is in slow wakeup mode and this erratum does not apply. In addition, this erratum has sporadic characteristic due to an internal asynchronous circuit. The drop of Vcore does not have an impact on specified device performance.

Workaround

If SVSL or SVML is required for application (to observe external disruptive events at Vcore pin) the slow wakeup mode has to be used to avoid unexpected SVSL/SVML events. This is achieved if the SVSL or the SVML is configured in "Normal" performance mode (not disabled and not in "Full" Performance Mode).

6.61 PMM20

Category

Function

Description

Workaround