SLAZ100AA October 2012 – May 2021 CC430F6127
CPU Module
Compiler-Fixed
LPM instruction can corrupt PC/SR registers
The PC and SR registers have the potential to be corrupted when:
- An instruction using register, absolute, indexed, indirect, indirect auto-increment, or symbolic mode is used to set the LPM bits AND (e.g. BIS &xyh, SR)
- This instruction is followed by a CALL or CALLA instruction
Upon servicing an interrupt service routine, the program counter (PC) is pushed twice onto the stack instead of the correct operation where the PC, then the SR registers are pushed onto the stack. This corrupts the SR and possibly the PC on RETI from the ISR.
Insert a NOP or __no_operation() intrinsic function between the instruction to enter low power mode and the CALL or CALLA instruction.
Refer to the table below for compiler-specific fix implementation information.
| IDE/Compiler | Version Number | Notes |
|---|---|---|
| IAR Embedded Workbench | IAR EW430 v6.20.1 until v6.40 | User is required to add the compiler or assembler flag option below. --hw_workaround=nop_after_lpm |
| IAR Embedded Workbench | IAR EW430 v6.40 or later | Workaround is automatically enabled |
| TI MSP430 Compiler Tools (Code Composer Studio) | v4.0 or later | User is required to add the compiler or assembler flag option below. --silicon_errata=CPU18 |
| MSP430 GNU Compiler (MSP430-GCC) | Not affected |