SLAZ100AA October 2012 – May 2021 CC430F6127
CPU Module
Compiler-Fixed
Using a certain instruction sequence to enter low power mode(s) affects the instruction width of the first instruction in an NMI ISR
If there is a pending NMI request when the CPU enters a low power mode (LPMx) using an instruction of Indexed source addressing mode, and that instruction is followed by a 20-bit wide instruction of Register source and destination addressing modes, the first instruction of the ISR is executed as a 20-bit wide instruction.
Example:
main:
...
MOV.W [indexed],SR ; Enter LPMx
MOVX.A [register],[register] ; 20-bit wide instruction
...
ISR_start:
MOV.B [indexed],[register] ; ERROR - Executed as a 20-bit instruction!
Note: [] indicates addressing mode
1. Insert a NOP or a __no_operation() intrinsic function following the instruction that enters the LPMx using indexed addressing mode
OR
2. Use a NOP or a __no_operation() intrinsic function as first instruction in the ISR
OR
3. Do not use the indexed mode to enter LPMx
Refer to the table below for compiler-specific fix implementation information.
| IDE/Compiler | Version Number | Notes |
|---|---|---|
| IAR Embedded Workbench | IAR EW430 v6.20 until v6.40 | User is required to add the compiler or assembler flag option below. --hw_workaround=nop_after_lpm |
| IAR Embedded Workbench | IAR EW430 v6.40 or later | Workaround is automatically enabled |
| TI MSP430 Compiler Tools (Code Composer Studio) | v4.1.3 or later | |
| MSP430 GNU Compiler (MSP430-GCC) | MSP430-GCC 4.9 build 167 |