米6体育平台手机版

SLAZ279AA October 2012 – May 2021 MSP430F5418

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6.104 UCS5

UCS Module

Function

Writes to UCSCTL0, UCSCTL1, UCSCTL2 and UCSCTL3 registers do not get updated

Description

During FLL operation, if two subsequent writes occur to the UCSCTL0-2 registers within one cycle of the DCO, the results are not updated and do not impact the FLL as expected.
Similarly, if two subsequent writes are performed to the UCSCTL3 register within one cycle of FLLREFCLK the results do not get updated.

Workaround

When writing to the UCSCTL0-2 registers, drive the CPU from a clock derived from DCO.
When writing to UCSCTL3, either avoid making subsequent writes, or insert a delay loop between the accesses to prevent them from occurring within the same FLLREFCLK cycle.

6.104 UCS5

Category

Function

Description

Workaround