米6体育平台手机版

SLAZ283AA October 2012 – May 2021 MSP430F5435

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6.102 UCS2

UCS Module

Function

LPM modes not entered properly when MCLK < ACLK

Description

When MCLK is sourced by XT1, XT2 or REFO clock sources and MCLK is slower than ACLK the low power modes are not entered properly.

This applies when the MCLK clock divider is greater than the ACLK clock divider setting.

Workaround

None

6.102 UCS2

Category

Function

Description

Workaround