米6体育平台手机版

SLAZ283AA October 2012 – May 2021 MSP430F5435

1
2
3
4
5
1. 6
2. 7
  1. 8
3. 9
10
1. 11
2. 12
3. 13
4. 14
5. 15
6. 16
7. 17
8. 18
9. 19
10. 20
11. 21
12. 22
13. 23
14. 24
15. 25
16. 26
17. 27
18. 28
19. 29
20. 30
21. 31
22. 32
23. 33
24. 34
25. 35
26. 36
27. 37
28. 38
29. 39
30. 40
31. 41
32. 42
33. 43
34. 44
35. 45
36. 46
37. 47
38. 48
39. 49
40. 50
41. 51
42. 52
43. 53
44. 54
45. 55
46. 56
47. 57
48. 58
49. 59
50. 60
51. 61
52. 62
53. 63
54. 64
55. 65
56. 66
57. 67
58. 68
59. 69
60. 70
61. 71
62. 72
63. 73
64. 74
65. 75
66. 76
67. 77
68. 78
69. 79
70. 80
71. 81
72. 82
73. 83
74. 84
75. 85
76. 86
77. 87
78. 88
79. 89
80. 90
81. 91
82. 92
83. 93
84. 94
85. 95
86. 96
87. 97
88. 98
89. 99
90. 100
91. 101
92. 102
93. 103
94. 104
95. 105
96. 106
97. 107
98. 108
99. 109
100. 110
101. 111
102. 112
103. 113
104. 114
105. 115
106. 116
107. 117
108. 118
109. 119
110. 120
111. 121
112. 122
113. 123
114. 124
115. 125
116. 126
117. 127
118. 128
129

6.74 PMM14

PMM Module

Function

Increasing the core level when SVS/SVM low side is configured in full-performance mode causes device reset

Description

When the SVS/SVM low side is configured in full performance mode (SVSMLCTL.SVSLFP = 1), the setting time delay for the SVS comparators is ~2us. When increasing the core level in full-performance mode; the core voltage does not settle to the new level before the settling time delay of the SVS/SVM comparator expires. This results in a device reset.

Workaround

When increasing the core level; enable the SVS/SVM low side in normal mode (SVSMLCTL.SVSLFP=0). This provides a settling time delay of approximately 150us allowing the core sufficient time to increase to the expected voltage before the delay expires.

6.74 PMM14

Category

Function

Description

Workaround