米6体育平台手机版

SLAZ616AA August 2014 – August 2021 MSP430FR68891

1
2
3
4
5
1. 6
2. 7
  1. 8
  2. 9
3. 10
11
1. 12
2. 13
3. 14
4. 15
5. 16
6. 17
7. 18
8. 19
9. 20
10. 21
11. 22
12. 23
13. 24
14. 25
15. 26
16. 27
17. 28
18. 29
19. 30
20. 31
21. 32
22. 33
23. 34
24. 35
25. 36
26. 37
27. 38
28. 39
29. 40
30. 41
31. 42
32. 43
33. 44
34. 45
35. 46
36. 47
37. 48
38. 49
39. 50
40. 51
41. 52
42. 53
43. 54
44. 55
45. 56
46. 57
58

6.3 ADC43

ADC Module

Function

DMA does not trigger at the end of an ADC12 sequence of channels

Description

The DMA transfer is triggered at the end of every ADC conversion when the ADC is configured to convert in a sequence of channels (ADC12CTL1.CONSEQ = 1 or 3.) This causes the DMA transfer to trigger prematurely after each ADC conversion instead of triggering only at the end of the conversion sequence.

Workaround

Design the application to expect the DMA trigger at the end of every ADC conversion. For example, if a block transfer at the end of the sequence is originally desired, configure the DMA in single transfer mode with size = length of the sequence. The DMA transfer occurs at each conversion, but the DMA interrupt will still occur at the end of the sequence.

6.3 ADC43

Category

Function

Description

Workaround