米6体育平台手机版

SLAZ618AA August 2014 – August 2021 MSP430FR69271

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6.45 USCI45

USCI Module

Function

Unexpected SPI clock stretching possible when UCxCLK is asynchronous to MCLK

Description

In rare cases, during SPI communication, the clock high phase of the first data bit may be stretched significantly. The SPI operation completes as expected with no data loss. This issue only occurs when the USCI SPI module clock (UCxCLK) is asynchronous to the system clock (MCLK).

Workaround

Ensure that the USCI SPI module clock (UCxCLK) and the CPU clock (MCLK) are synchronous to each other.

6.45 USCI45

Category

Function

Description

Workaround