SLAZ679R August 2015 – August 2021 MSP430FR2311
USCI Module
Functional
Unexpected SPI clock stretching possible when UCxCLK is asynchronous to MCLK
In rare cases, during SPI communication, the clock high phase of the first data bit may be stretched significantly. The SPI operation completes as expected with no data loss. This issue only occurs when the USCI SPI module clock (UCxCLK) is ACLK and it is asynchronous to the system clock (MCLK).
Ensure that the USCI SPI module clock (UCxCLK) and the CPU clock (MCLK) are synchronous to each other.