SLAZ754 December 2023 MSPM0L1304-Q1 , MSPM0L1305-Q1 , MSPM0L1306-Q1
Peripheral registers are still accessible after disabling PWREN register
Rev C
When disabling the power of a peripheral by setting the PWREN register to 0, the peripheral’s registers may appear to retain data values if read. Reading or writing to the registers when PWREN is 0 has no affect as the peripheral has no effect.
The following peripherals are affected: comparator (COMP), operational amplifier (OPA), TimerA, TimerG, general-purpose input/output (GPIO), and windowed watchdog timer (WWDT).
When the PWREN register of the peripheral is set to 0, the values of the associated registers should be disregarded or considered invalid.