Revisions Affected

Rev C

Details

When MFCLK is enabled AND SYSOSC is using the frequency correction loop (FCL) mode AND the STOP1 low power operating mode is used, THEN the MFCLK may drift by 2 cycles when SYSOSC shifts from 4MHz back to 32MHz (either upon exit from STOP1 to RUN mode or upon an asynchronous fast clock request that forces SYSOSC to 32MHz).

Workaround1

Use STOP0 mode instead of STOP1 mode. There is no MFCLK drift when STOP0 mode is used.

Workaround2

Do not use SYSOSC in the FCL mode (leave FCL disabled) when using STOP1.