SLLA515 November 2020 SN6501-Q1
The failure mode distribution estimation for SN6501-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| D1 and/or D2 FET stuck off | 48% |
| D1 and/or D2 FET stuck ON | 38% |
| D1 and/or D2 output not in timing or voltage specification | 12% |
| D1 and/or D2 output undetermined | 2% |