Fail-safe mode can be disabled through a SPI write by setting the FSM_DIS bit of the FSM_CONFIG register (8’h17[0]) to 1b. If fail-safe mode is enabled, the device enters fail-safe mode if any of these events occur:

• UV_CC (V_CC undervoltage)
• OV_CC (V_CC overvoltage)
• TSD (thermal shutdown)
• V_CCSC (V_CC short-circuit)
• SWE timeout in standby mode

To successfully transition from fail-safe mode to normal mode, all of these faults must be cleared. Exiting this mode requires a wake event to take place, which transitions the device to restart mode. If faults are cleared, transition to normal mode can take place as described in Section 3.2.2 and Section 3.2.3. If faults are not cleared, the device will enter sleep mode after the SWE timer expires.

Each time the device enters fail-safe mode, the fail-safe mode counter is incremented. This counter (8’h18[3:0]) should be regularly set to 0 by a SPI command. Otherwise, if the counter reaches the limit (set in 8’h18[7:4]), then the action prescribed in FSM_CNTR_ACT (8’h17[7:4]) will take place.

Additionally, FS_STAT (8’h17[3:1]) provides the reason the device entered fail-safe mode, and SWE_TIMER_SET (8’h1C[6:3]) sets the length of time the SWE timer can support, ranging from 30 seconds to 10 minutes (defaulted to 5 minutes).