SLLA600 October 2022 THVD8000 , THVD8010

1 Standard THVD80x0 Design Process and Assumptions

The standard architecture of a Power Bus application is shown in Figure 1-1. Please note that the termination resistor between A and B is not shown but is a recommended and common addition to help mitigate potential EMI/EMC issues due to reflections.

Figure 1-1 THVD80x0 Standard Approach with Two Nodes Shown

In the standard design process the THVD80x0 is assumed to see the power load and the power source as AC ground – this assumption is valid in DC power systems as most DC power sources have output bulk capacitance that filter the high frequency data signal from the THVD80x0 Device. An amended diagram with the AC Ground shown in Figure 1-2.

Figure 1-2 THVD80x0 Standard Approach, Including AC Ground, with Two Nodes Shown

Since PowerBus still relies on the RS-485 standard the impedance from either the A or B line to ground can be calculated with Equation 1 for terminated systems (assuming two 120 Ω terminations in the system) and Equation 2 for unterminated systems.

Equation 1.

\frac{1}{\sum_{2}^{N} \frac{1}{Z_{i n_{i}} + Z_{C i}} + \sum_{1}^{N} \frac{1}{Z_{L i}}} + Z_{C 1} \geq 375 Ω

Equation 2.

\frac{1}{\sum_{2}^{N} \frac{1}{Z_{i n_{i}} + Z_{C i}} + \sum_{1}^{N} \frac{1}{Z_{L i}}} + Z_{C 1} \geq 60 Ω

The first summation on the bottom left side is the input impedance plus series capacitance inductance on the either the A or B line. It starts at node 2, as node 1 is the transmitting node and can be excluded in this calculation, and counts all other nodes on the line (from 2 to N). The second summation is the effective impedance of the inductors on the A or B line. The final term is the first series capacitance the transmitter sends its signal through and can be added to the rest of the impedance calculation. The input impedance for the THVD80x0 Family of Devices can be approximated to 96 KΩ and the capacitor impedance and inductor impedance are shown in Equation 3 and Equation 4 respectively.

Equation 3.

Z_{L} = 2 \times π \times f_{m o d} \times L

Equation 4.

Z_{C} = \frac{1}{2 \times π \times f_{m o d} \times C}

Where the modulation frequency is the frequency of the data signal set through a setting resistor on the THVD80x0 Family of Devices. It is easiest to have all inductors be the same value as well as all the capacitors having the same value. This simplifies the equations Equation 1 and Equation 2 to what is seen in Equation 5 and Equation 6 respectively

Equation 5.

\frac{1}{\frac{N - 1}{Z_{C} + Z_{i n}} + \frac{N}{Z_{L}}} + Z_{C} \geq 375 Ω

Equation 6.

\frac{1}{\frac{N - 1}{Z_{C} + Z_{i n}} + \frac{N}{Z_{L}}} + Z_{C} \geq 60 Ω

Capacitors should be designed to have a max impedance at the modulation frequency of 5 Ω whereas the inductors need to be designed around Equation 5 for terminated systems and Equation 6 for unterminated systems. The capacitor and inductor conditions are shown in equations Equation 7, Equation 8, and Equation 9 respectively.

Equation 7.

C \geq \frac{1}{2 \times π \times f_{m o d} \times 5}

Equation 8.

L > = \frac{N}{2 \times π \times f_{m o d} \times (\frac{1}{375 - Z_{C}} - \frac{N - 1}{Z_{C} + Z_{i n}})}

Equation 9.

L > = \frac{N}{2 \times π \times f_{m o d} \times (\frac{1}{60 - Z_{C}} - \frac{N - 1}{Z_{C} + Z_{i n}})}

The impact of the input impedance can be neglected in many applications – regardless of frequency as its impact is relatively small in low node count systems. The simplified equations are shown in Equation 10 and Equation 11 respectively.

Equation 10.

L > = \frac{N}{2 \times π \times f_{m o d} \times (\frac{1}{375 - Z_{C}})}

Equation 11.

L > = \frac{N}{2 \times π \times f_{m o d} \times (\frac{1}{60 - Z_{C}})}

Where the error between simplified equations in Equation 10 and Equation 11 and the full equations in Equation 8 and Equation 9 are given by Equation 12 and Equation 13 respectively.

Equation 12.

E r r o r = (\frac{1}{375 - Z_{C}} - \frac{N - 1}{Z_{C} + Z_{i n}}) \times ((375 - Z_{C}) - \frac{1}{\frac{1}{375 - Z_{C}} - \frac{N - 1}{Z_{C} + Z_{i n}}})

Equation 13.

E r r o r = (\frac{1}{60 - Z_{C}} - \frac{N - 1}{Z_{C} + Z_{i n}}) \times ((60 - Z_{C}) - \frac{1}{\frac{1}{60 - Z_{C}} - \frac{N - 1}{Z_{C} + Z_{i n}}}

A summary of percentage error when using the simplified equations compared the more correct equations are shown in Table 1-1. This is assuming capacitor impedance is 5 Ω and input impedance is 96 KΩ.

Table 1-1 Summary of Percentage Error with Simplified Equations

\|Error Percentage\|	Number of Nodes (Terminated)	Number of Nodes (Unterminated)
<0.1%	Not Possible	2
<0.5%	2	9
<1%	3	18
<5%	13	88
<10%	26	175

With a basic understanding of the design process and the assumptions (along with their justification) for DC power systems – how to modify the system to support AC power can now be explained.