SLLSEJ2G July   2015  – March 2020

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      DP159 Mother Board Application Structure
      2.      DP159 Dongle Application Structure
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  AUX, DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 AUX Switching Characteristics (Only for RGZ Package)
    12. 7.12 HPD Switching Characteristics
    13. 7.13 DDC and I2C Switching Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Implementation
      2. 9.3.2 Operation Timing
      3. 9.3.3 I2C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)
      4. 9.3.4 Input Lane Swap and Polarity Working
      5. 9.3.5 Main Link Inputs
      6. 9.3.6 Main Link Inputs Debug Tools
      7. 9.3.7 Receiver Equalizer
      8. 9.3.8 Termination Impedance Control
      9. 9.3.9 TMDS Outputs
        1. 9.3.9.1 Pre-Emphasis/De-Emphasis
    4. 9.4 Device Functional Modes
      1. 9.4.1 Retimer Mode
      2. 9.4.2 Redriver Mode
      3. 9.4.3 DDC Training for HDMI2.0 Data Rate Monitor
      4. 9.4.4 DDC Functional Description
    5. 9.5 Register Maps
      1. 9.5.1 DP-HDMI Adaptor ID Buffer
      2. 9.5.2 Local I2C Interface Overview
      3. 9.5.3 I2C Control Behavior
      4. 9.5.4 I2C Control and Status Registers
        1. 9.5.4.1 Bit Access Tag Conventions
        2. 9.5.4.2 CSR Bit Field Definitions
          1. 9.5.4.2.1 ID Registers
          2. 9.5.4.2.2 Misc Control
          3. 9.5.4.2.3 HDMI Control
          4. 9.5.4.2.4 Equalization Control Register
          5. 9.5.4.2.5 EyeScan Control Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Use Case of SNx5DP159
      2. 10.1.2 DDC Pullup Resistors
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 Compliance Testing
  11. 11Power Supply Recommendations
    1. 11.1 Power Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

7.8 AUX, DDC, and I2C Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CIO Input capacitance AUX data rate = 1-MHz 10 pF
CAC AUX AC coupling capacitance 75 200 nF
DR(AUX) Data rate of the AUX channel input 0.8 1 1.2 Mbps
VI-DC(AUX) DC input voltage on AUX channel, AUX_SRCp/n: 100-kΩ pull up to 3.6 V but differential common mode is 2 V or less. -0.5 3.6 V
VAUX_DIFF_PP_TX Peak-to-peak differential voltage at TX pins VAUX_DIFF_PP = 2 × |VAUXP – VAUXN| 0.29 1.38 V
VAUX_DIFF_PP_RX Peak-to-peak differential voltage at RX pins VAUX_DIFF_PP = 2 × |VAUXP – VAUXN| 0.14 1.36 V
VAUX_DC_CM AUX channel DC common mode voltage 0 2 V
IAUX_SHORT AUX channel short circuit current limit 90 mA
VI-DC SCL/SDA_SNK DC input voltage –0.3 5.6 V
SCL/SDA_CTL, SCL/SDA_SRC DC input voltage -0.3 3.6 V
VIL SCL/SDA_SNK, SCL/SDA_SRC Low level input voltage 0.3 x VCC V
SCL/SDA_CTL Low level input voltage 0.3 x VCC V
VIH SCL/SDA_SNK high level input voltage 3 V
SCL/SDA_SRC high level input voltage 0.7 x VCC V
SCL/SDA_CTL high level input voltage 0.7 x VCC V
VOL SCL/SDA_CTL, SCL/SDA_SRC low-level output voltage I0 = 3-mA and VCC > 2-V 0.4 V
I0 = 3-mA and VCC < 2-V 0.2 VCC V
fSCL SCL clock frequency fast I2C mode for local I2C control 400 kHz
Cbus Total capacitive load for each bus line (DDC and local I2C pins) 400 pF
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