SLLSEJ2G July 2015 – March 2020
PRODUCTION DATA.
| ADDRESS | BITS | DEFAULT | DESCRIPTION | ACCESS |
|---|---|---|---|---|
| 0Eh | 7:4 | 4’b0000 | PV_SYNC[3:0]. Pattern timing pulse. This field is updated for 8UI once every cycle of the PRBS generator. 1 bit per lane. | R |
| 3:0 | 4’b0000 | PV_LD[3:0]. Load pattern-verifier controls into RX lanes. When asserted high, the PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values are enabled into the corresponding RX lane. These values are then latched and held when PV_LD[n] is subsequently de-asserted low. 1 bit per lane. | RWU | |
| 0Fh | 7:4 | 4’b0000 | PV_FAIL[3:0]. Pattern verification mismatch detected. 1 bit per lane. | RU |
| 3:0 | 4’b0000 | PV_TIP[3:0]. Pattern search/training in progress. 1 bit per lane. | RU | |
| 10h | 7 | 1’b0 | PV_CP20. Customer pattern length 20 or 16 bits.
0 – 16 bits 1 – 20 bits |
RW |
| 6 | 1’b0 | Reserved | R | |
| 5:3 | 3’b000 | PV_LEN[2:0]. PRBS pattern length
000 – PRBS7 001 – PRBS11 010 – PRBS23 011 – PRBS31 100 – PRBS15 101 – PRBS15 110 – PRBS20 111 – PRBS20 |
RW | |
| 2:0 | 3’b000 | PV_SEL[24:0]. Pattern select control
000 – Disabled 001 – PRBS 010 – Clock 011 – Custom 1xx – Timing only mode with sync pulse spacing defined by PV_LEN |
RW | |
| 11h | 7:0 | ‘h00 | PV_CP[7:0]. Custom pattern data. | RW |
| 12h | 7:0 | ‘h00 | PV_CP[15:8]. Custom pattern data. | RW |
| 13h | 7:4 | 4’b0000 | Reserved | R |
| 3:0 | 4’b0000 | PV_CP[19:16]. Custom pattern data. Used when PV_CP20 = 1’b1. | RW | |
| 14h | 7:3 | 5’b00000 | Reserved | R |
| 2:0 | 3’b000 | PV_THR[2:0]. Pattern-verifier retain threshold. | RW | |
| 15h | 7 | 1'b0 | DESKEW_CMPLT: Indicates TMDS lane deskew has completed when high | R |
| 6:5 | 2’b00 | Reserved | R | |
| 4 | 1’b0 | BERT_CLR. Clear BERT counter (on rising edge). | RSU | |
| 3 | 1’b0 | TST_INTQ_CLR. Clear latched interrupt flag. | RSU | |
| 2:0 | 3’b000 | TST_SEL[2:0]. Test interrupt source select. | RW | |
| 16h | 7:4 | 4’b0000 | PV_DP_EN[3:0]. Enabled datapath verified based on DP_TST_SEL, 1 bit per lane. | RW |
| 3 | 1’b0 | Reserved | R | |
| 2:0 | 3'b000 | DP_TST_SEL[2:0] Selects pattern reported by BERT_CNT[11:0], TST_INT[0] and TST_INTQ[0]. PV_DP_EN is non-zero
000 – TMDS disparity or data errors 001 – FIFO errors 010 – FIFO overflow errors 011 – FIFO underflow errors 100 – TMDS deskew status 101 – Reserved 110 – Reserved 111 – Reserved |
RW | |
| 17h | 7:4 | 4’b0000 | TST_INTQ[3:0]. Latched interrupt flag. 1 bit per lane | RU |
| 3:0 | 4’b0000 | TST_INT[3:0]. Test interrupt flag. 1 bit per lane. | RU | |
| 18h | 7:0 | ‘h00 | BERT_CNT[7:0]. BERT error count. Lane 0 | RU |
| 19h | 7:4 | 4’b0000 | Reserved | R |
| 3:0 | 4’b0000 | BERT_CNT[11:8]. BERT error count. Lane 0 | RU | |
| 1Ah | 7:0 | ‘h00 | BERT_CNT[19:12]. BERT error count. Lane 1 | RU |
| 1Bh | 7:4 | 4’b0000 | Reserved | R |
| 3:0 | 4’b0000 | BERT_CNT[23:20]. BERT error count. Lane 1 | RU | |
| 1Ch | 7:0 | ‘h00 | BERT_CNT[31:24]. BERT error count. Lane 2 | RU |
| 1Dh | 7:4 | 4’b0000 | Reserved | R |
| 3:0 | 4’b0000 | BERT_CNT[35:32]. BERT error count. Lane 2 | RU | |
| 1Eh | 7:0 | ‘h00 | BERT_CNT[19:12]. BERT error count. Lane 3 | RU |
| 1Fh | 7:4 | 4’b0000 | Reserved | R |
| 3:0 | ‘h00 | BERT_CNT[23:20]. BERT error count. Lane 3 | RU | |
| 20h | 7:4 | 4’b0000 | Reserved | R |
| 3 | 1'b1 | AUX_TX_SR Slew Rate Control for AUX Output | RW | |
| 2:0 | 3'b010 | AUX_SWING; Swing Control for AUX Output
000 – 270 mV 001 – 355 mV 010 – 450 mV 011 – 535 mV 100 – 625 mV 101 – 710 mV 110 – 800 mV 111 – Not allowed |
RW |