SLLSEJ2G July 2015 – March 2020
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| REDRIVER MODE | ||||||
| DR | Data rate (Automatic Mode) | 250 | 1000 | Mbps | ||
| DR | Data rate (full redriver mode) | 250 | 6000 | Mbps | ||
| tPLH | Propagation delay time (low to high) | 250 | 600 | ps | ||
| tPHL | Propagation delay time (high to low) | 250 | 800 | ps | ||
| tT1 | Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. | SLEW_CTL = H; TX_TERM_CTL = L; PRE_SEL = NC; OE = H; DR = 6 Gbps | 45 | ps | ||
| tT2 | SLEW_CTL = L; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps | 65 | ||||
| tT3 | SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; CLK 150MHz | 100 | ||||
| tSK1(T) | Intra-pair output skew | SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; | 40 | ps | ||
| tSK2(T) | Inter-pair output skew | SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; | 100 | ps | ||
| tJITD1(1.4b) | Total output data jitter | DR = 2.97 Gbps, HDMI_SEL/A1 = NC, EQ_SEL/A0 = NC; PRE_SEL = NC; SLEW_CTL = H OE = H.
See Figure 10 at TTP3 |
0.2 | Tbit | ||
| tJITD1(2.0) | Total output data jitter | 3.4Gbps < Rbit ≤ 3.712Gps SLEW_CTL = H; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H | 0.4 | Tbit | ||
| 3.712Gbps < Rbit < 5.94Gbps SLEW_CTL = H; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H | -0.0332Rbit2 +0.2312 Rbit + 0.1998 | Tbit | ||||
| 5.94Gbps ≤ Rbit ≤ 6.0Gbps SLEW_CTL = H; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H | 0.8 | Tbit | ||||
| tJITC1(1.4b) | Total output clock jitter | CLK = 297 MHz | 0.25 | Tbit | ||
| tJITC1(2.0) | Total output clock jitter | DR = 6Gbps: CLK = 150 MHz | 0.3 | Tbit | ||
| RETIMER MODE | ||||||
| dR | Data rate (Full retimer mode) | 0.25 | 6 | Gbps | ||
| dR | Data rate (Automatic mode) | 1.0 | 6 | Gbps | ||
| dXVR | Automatic redriver to retimer crossover | Measured with input signal applied from 0 to 200 mVpp | .75 | 1.0 | 1.25 | Gbps |
| fCROSSOVER | Crossover frequency hysteresis | 250 | MHz | |||
| PLLBW | Data retimer PLL bandwidth | Default loop bandwidth setting | .4 | 1 | MHz | |
| tACQ | Input clock frequency detection and retimer acquisition time | 180 | μs | |||
| IJT1 | Input clock jitter tolerance | Tested when data rate > 1.0 Gbps | 0.3 | Tbit | ||
| tT1 | Transition time (rise and fall time); measured at 20% and 80% levels for data lanes. TMDS clock meets tT3 for all three times. | SLEW_CTL = H; TX_TERM_CTL = L; PRE_SEL = NC; OE = H; DR = 6 Gbps | 45 | ps | ||
| tT2 | SLEW_CTL = L; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps | 65 | ||||
| tT3 | SLEW_CTL = NC; TX_TERM_CTL = NC; PRE_SEL = NC; OE = H; DR = 6 Gbps; CLK = 150 MHz | 100 | ||||
| tDCD | OUT_CLK ± duty cycle | 40% | 50% | 60% | ||
| tSK_INTER | Inter-pair output skew | Default setting for internal inter-pair skew adjust, HDMI_SEL/A1 = NC | 0.2 | Tch | ||
| tSK_INTRA | 0.15 | Tbit | ||||
| tJITC1(1.4b) | Total output clock jitter | CLK = 297 MHz | 0.25 | Tbit | ||
| tJITC1(2.0) | Total output clock jitter | DR = 6Gbps: CLK = 150 MHz | 0.3 | Tbit | ||
| tJITD2 | Total output data jitter | 3.4 Gbps < Rbit ≤ 3.712 Gbps | 0.4 | Tbit | ||
| 3.712 Gbps < Rbit < 5.94 Gbps | See (1) | |||||
| 5.94 Gbps ≤ Rbit ≤ 6.0 Gbps | 0.6 | |||||
| VOD_range | Total TMDS data lanes output differential voltage | 3.4 Gbps < Rbit ≤ 3.712 Gbps | 335 | mV | ||
| 3.712 Gbps < Rbit < 5.94 Gbps | See (2) | |||||
| 5.94 Gbps ≤ Rbit ≤ 6.0 Gbps | 150 | |||||