SLLSER8J June   2017  – August 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Function
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications for D Package
    7. 6.7  Insulation Specifications for DWV Package
    8. 6.8  Safety-Related Certifications For D Package
    9. 6.9  Safety-Related Certifications For DWV Package
    10. 6.10 Safety Limiting Values
    11. 6.11 Electrical Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 7.1.1 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN+ and IN– Input Filter
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
      3. 9.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 9.2.3.1 Selecting a VCC1 Capacitor
        2. 9.2.3.2 Selecting a VCC2 Capacitor
        3. 9.2.3.3 Application Circuits with Output Stage Negative Bias
      4. 9.2.4 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

6.7 Insulation Specifications for DWV Package

PARAMETERTEST CONDITIONSVALUEUNIT
DWV
CLRExternal Clearance(1)Shortest pin–to-pin distance through air≥ 8.5mm
CPGExternal Creepage(1)Shortest pin–to-pin distance across the package surface≥ 8.5mm
DTIDistance through the insulationMinimum internal gap (internal clearance)> 21µm
CTIComparative tracking indexDIN EN 60112 (VDE 0303–11); IEC 60112> 600V
Material GroupAccording to IEC 60664–1I
Overvoltage category per IEC 60664-1
Rated mains voltage ≤ 600VRMSI-III
Rated mains voltage ≤ 1000VRMSI-II
DIN V VDE 0884–11: 2017–01(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)2121VPK
VIOWMMaximum isolation working voltageAC voltage (sine wave); time dependent dielectric breakdown (TDDB) test1500VRMS
DC Voltage2121VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM, t = 60 s (qualification) ;
VTEST = 1.2 × VIOTM, t = 1 s (100% production)		7000VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 62368-1, 1.2/50-µs waveform, VTEST = 1.6 × VIOSM (qualification)8000VPK
qpdApparent charge (4)Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s
Vpd(m) = 1.2 × VIORM, tm = 10 s		≤ 5pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s		≤ 5
Method b1: At routine test (100% production) and preconditioning (type test),
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s		≤ 5
CIOBarrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz1.2pF
RIOIsolation resistance, input to output(5)VIO = 500 V,  TA = 25°C> 1012Ω
VIO = 500 V,  100°C ≤ TA ≤ 125°C> 1011
VIO = 500 V at TS = 150°C> 109
Pollution degree2
Climatic category40/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO, t = 1 s (100% production)5000VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |