SLLSER8J June   2017  – August 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Function
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications for D Package
    7. 6.7  Insulation Specifications for DWV Package
    8. 6.8  Safety-Related Certifications For D Package
    9. 6.9  Safety-Related Certifications For DWV Package
    10. 6.10 Safety Limiting Values
    11. 6.11 Electrical Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 7.1.1 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN+ and IN– Input Filter
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
      3. 9.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 9.2.3.1 Selecting a VCC1 Capacitor
        2. 9.2.3.2 Selecting a VCC2 Capacitor
        3. 9.2.3.3 Application Circuits with Output Stage Negative Bias
      4. 9.2.4 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

6.6 Insulation Specifications for D Package

PARAMETER TEST CONDITIONS VALUE UNIT
D
CLR External Clearance(1) Shortest pin–to-pin distance through air ≥ 4 mm
CPG External Creepage(1) Shortest pin–to-pin distance across the package surface ≥ 4 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) > 21 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303–11); IEC 60112 > 400 V
Material Group According to IEC 60664–1 II
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150VRMS I-IV
Rated mains voltage ≤ 300VRMS I-III
DIN V VDE 0884–11: 2017–01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 990(6) VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test 700(6) VRMS
DC Voltage 990(6) VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification);
VTEST = 1.2 × VIOTM, t = 1 s (100% production)		 4242 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50-µs waveform, VTEST = 1.3 × VIOSM (qualification) 4242 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s
Vpd(m) = 1.2 × VIORM, tm = 10 s		 ≤ 5 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s		 ≤ 5
Method b1: At routine test (100% production) and preconditioning (type test),
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.5 × VIORM, tm = 1 s		 ≤ 5
CIO Barrier capacitance, input to output(5)  VIO = 0.4 × sin (2πft), f = 1 MHz 1.2 pF
RIO Isolation resistance, input to output(5) VIO = 500 V,  TA = 25°C > 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO, t = 1 s (100% production) 3000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
(6) System isolation working voltages need to be verified according to application parameters.
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