SLLSER8J June   2017  – August 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Function
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications for D Package
    7. 6.7  Insulation Specifications for DWV Package
    8. 6.8  Safety-Related Certifications For D Package
    9. 6.9  Safety-Related Certifications For DWV Package
    10. 6.10 Safety Limiting Values
    11. 6.11 Electrical Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 7.1.1 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN+ and IN– Input Filter
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
      3. 9.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 9.2.3.1 Selecting a VCC1 Capacitor
        2. 9.2.3.2 Selecting a VCC2 Capacitor
        3. 9.2.3.3 Application Circuits with Output Stage Negative Bias
      4. 9.2.4 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

6.12 Switching Characteristics

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Output-signal rise time UCC5320SC, UCC5320EC, and UCC5310MC, CLOAD = 1 nF 12 28 ns
UCC5390SC, UCC5350SB, UCC5390EC, and UCC5350MC, CLOAD = 1 nF 10 26 ns
tf Output-signal fall time UCC5320SC and UCC5320EC, CLOAD = 1 nF 10 25 ns
UCC5310MC, CLOAD = 1 nF 10 26 ns
UCC5390SC, UCC5350SB, UCC5390EC, and UCC5350MC, CLOAD = 1 nF 10 22 ns
tPLH Propagation delay
(default versions), high		 UCC5320SC and UCC5320EC, CLOAD = 100 pF 60 72 ns
UCC5310MC, CLOAD = 100 pF 60 75 ns
UCC5390SC, UCC5350SB, UCC5390EC, and UCC5350MC, CLOAD = 100 pF 65 100 ns
tPHL Propagation delay
(default versions), low		 UCC5320CS and UCC5320EC, CLOAD = 100 pF 60 75 ns
UCC5310MC, CLOAD = 100 pF 60 75 ns
UCC5390SC, UCC5350SB, UCC5390EC, and UCC5350MC, CLOAD = 100 pF 65 100 ns
tUVLO1_rec UVLO recovery delay of VCC1 See Figure 8-9 30 µs
tUVLO2_rec UVLO recovery delay of VCC2 See Figure 8-9 50 µs
tPWD Pulse width distortion
|tPHL – tPLH|		 UCC5320SC and UCC5320EC, CLOAD = 100 pF 1 20 ns
UCC5310MC, CLOAD = 100 pF 1 20 ns
UCC5390SC, UCC5350SB, and UCC5390EC, CLOAD = 100 pF 1 20 ns
UCC5350MC, CLOAD = 100 pF 1 20 ns
tsk(pp) Part-to-part skew(1) UCC5320SC and UCC5320EC, CLOAD = 100 pF 1 25 ns
UCC5310MC, CLOAD = 100 pF 1 25 ns
UCC5390SC, UCC5350SB, and UCC5390EC, CLOAD = 100 pF 1 25 ns
UCC5350MC, CLOAD = 100 pF 1 25 ns
CMTI Common-mode transient immunity PWM is tied to GND or VCC1, VCM = 1200 V 100 120 kV/µs
(1) tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads guaranteed by characterization.
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