SLLSER8J June   2017  – August 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Function
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications for D Package
    7. 6.7  Insulation Specifications for DWV Package
    8. 6.8  Safety-Related Certifications For D Package
    9. 6.9  Safety-Related Certifications For DWV Package
    10. 6.10 Safety Limiting Values
    11. 6.11 Electrical Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 7.1.1 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN+ and IN– Input Filter
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
      3. 9.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 9.2.3.1 Selecting a VCC1 Capacitor
        2. 9.2.3.2 Selecting a VCC2 Capacitor
        3. 9.2.3.3 Application Circuits with Output Stage Negative Bias
      4. 9.2.4 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Function

UCC5310 UCC5320 UCC5350 UCC5390 UCC5320S, UCC5350SB, and UCC5390S 8-Pin SOICTop View Figure 5-1 UCC5320S, UCC5350SB, and UCC5390S 8-Pin SOICTop View
UCC5310 UCC5320 UCC5350 UCC5390 UCC5310M and UCC5350M 8-Pin SOICTop View Figure 5-2 UCC5310M and UCC5350M 8-Pin SOICTop View
UCC5310 UCC5320 UCC5350 UCC5390 UCC5320E and UCC5390E 8-Pin SOICTop View Figure 5-3 UCC5320E and UCC5390E 8-Pin SOICTop View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
UCC53x0S UCC53x0M UCC53x0E
CLAMP — 7 — I Active Miller-clamp input found on the UCC53x0M used to prevent false turnon of the power switches.
GND1 4 4 4 G Input ground. All signals on the input side are referenced to this ground.
GND2 — — 7 G Gate-drive common pin. Connect this pin to the IGBT emitter. UVLO referenced to GND2 in the UCC53x0E.
IN+ 2 2 2 I Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS input threshold. This pin is pulled low internally if left open. Use Table 8-4 to understand the input and output logic of these devices.
IN– 3 3 3 I Inverting gate-drive voltage control input. The IN– pin has a CMOS input threshold. This pin is pulled high internally if left open. Use Table 8-4 to understand the input and output logic of these devices.
OUT — 6 6 O Gate-drive output for UCC53x0E and UCC53x0M versions.
OUTH 6 — — O Gate-drive pull-up output found on the UCC53x0S.
OUTL 7 — — O Gate-drive pull-down output found on the UCC53x0S.
VCC1 1 1 1 P Input supply voltage. Connect a locally decoupled capacitor to GND. Use a low-ESR or ESL capacitor located as close to the device as possible.
VCC2 5 5 5 P Positive output supply rail. Connect a locally decoupled capacitor to VEE2. Use a low-ESR or ESL capacitor located as close to the device as possible.
VEE2 8 8 8 P Negative output supply rail for E version, and GND for S and M versions. Connect a locally decoupled capacitor to GND2 for E version. Use a low-ESR or ESL capacitor located as close to the device as possible.
(1) P = Power, G = Ground, I = Input, O = Output
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