SLLSEY7F
June 2017 – April 2020
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Application Diagram
ISO121x Devices Reduce Board Temperatures vs Traditional Solutions
4
Revision History
5
Pin Configuration and Functions
Pin Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
Safety Limiting Values
6.9
Electrical Characteristics—DC Specification
6.10
Switching Characteristics—AC Specification
6.11
Insulation Characteristics Curves
6.12
Typical Characteristics
7
Parameter Measurement Information
7.1
Test Circuits
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Sinking Inputs
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Setting Current Limit and Voltage Thresholds
9.2.1.2.2
Thermal Considerations
9.2.1.2.3
Designing for 48-V Systems
9.2.1.2.4
Designing for Input Voltages Greater Than 60 V
9.2.1.2.5
Surge, ESD, and EFT Tests
9.2.1.2.6
Multiplexing the Interface to the Host Controller
9.2.1.2.7
Status LEDs
9.2.1.3
Application Curve
9.2.2
Sourcing Inputs
9.2.3
Sourcing and Sinking Inputs (Bidirectional Inputs)
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Development Support
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Related Links
12.4
Receiving Notification of Documentation Updates
12.5
Community Resource
12.6
Trademarks
12.7
Electrostatic Discharge Caution
12.8
Glossary
13
Mechanical, Packaging, and Orderable Information
7.1
Test Circuits
Figure 10.
Switching Characteristics Test Circuit and Voltage Waveforms
Figure 11.
Input Current and Voltage Threshold Test Circuit
Figure 12.
Enable and Disable Propagation Delay Time Test Circuit and Waveform—Logic Low State
Figure 13.
Enable and Disable Propagation Delay Time Test Circuit and Waveform—Logic High State
1.
Pass Criterion: The output must remain stable.
Figure 14.
Common-Mode Transient Immunity Test Circuit
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