SLLSF86C May   2018  – March 2022

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description Continued
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  Recommended Operating Conditions
    3. 8.3  Thermal Information
    4. 8.4  Power Ratings
    5. 8.5  Insulation Specifications
    6. 8.6  Safety-Related Certifications
    7. 8.7  Safety Limiting Values
    8. 8.8  Electrical Characteristics
    9. 8.9  Supply Current Characteristics at VISOOUT = 3.3 V
    10. 8.10 Supply Current Characteristics at  VISOOUT = 5 V
    11. 8.11 Switching Characteristics at VISOOUT = 3.3 V
    12. 8.12 Switching Characteristics at VISOOUT = 5 V
    13. 8.13 Insulation Characteristics Curves
    14. 8.14 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Power Isolation
    3. 10.3 Signal Isolation
    4. 10.4 RS-485
    5. 10.5 Functional Block Diagram
    6. 10.6 Feature Description
      1. 10.6.1 Power-Up and Power-Down Behavior
      2. 10.6.2 Protection Features
      3. 10.6.3 Failsafe Receiver
      4. 10.6.4 Glitch-Free Power Up and Power Down
    7. 10.7 Device Functional Modes
    8. 10.8 Device I/O Schematics
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Data Rate, Bus Length and Bus Loading
        2. 11.2.2.2 Stub Length
        3. 11.2.2.3 Insulation Lifetime
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 Support Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

8.11 Switching Characteristics at VISOOUT = 3.3 V

Min / Max specifications are over recommended operating conditions, typical values are at VDD = VIO = 3.3 V, MODE=GND2 ( VISOOUT= 3.3V), GND1 = GNDIO, GND2 = GISOIN, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver: 500-kbps device (ISOW1412)
tr, tf Differential output rise time and fall time RL = 54 Ω, CL = 50 pF, see Figure 9-3 190 300 600 ns
tPHL, tPLH Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 9-3 450 610 ns
PWD Pulse width distortion(1), |tPHL - tPLH| RL = 54 Ω, CL = 50 pF, see Figure 9-3 3 40 ns
tPHZ, tPLZ Disable time See Figure 9-5 and Figure 9-6 56 200 ns
tPZH, tPZL Enable time See Figure 9-5 and Figure 9-6 280 600 ns
Receiver: 500-kbps device (ISOW1412)
tr, tf Output rise time and fall time CL = 15 pF, see Figure 9-7 4 ns
tPHL, tPLH Propagation delay CL = 15 pF, see Figure 9-7 60 135 ns
PWD Pulse width distortion(1), |tPHL - tPLH| CL = 15 pF, see Figure 9-7 2 15 ns
tPHZ, tPLZ Disable time See Figure 9-8 and Figure 9-9 9 30 ns
tPZH, tPZL Enable time See Figure 9-8 and Figure 9-9 8 30 ns
Driver: 12-Mbps device (ISOW1432)
tr, tf Differential output rise time and fall time RL = 54 Ω, CL = 50 pF, see Figure 9-3 6 15 25 ns
tPHL Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 9-3 49 125 ns
tPLH Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 9-3 49 125 ns
tPHL, tPLH Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 9-3 52 125 ns
PWD Pulse width distortion(1), |tPHL - tPLH| RL = 54 Ω, CL = 50 pF, see Figure 9-3 1 10 ns
tPHZ Disable time See Figure 9-5 and Figure 9-6 35 125 ns
tPLZ Disable time See Figure 9-5 and Figure 9-6 35 125 ns
tPHZ, tPLZ Disable time See Figure 9-5 and Figure 9-6 36 125 ns
tPZH Enable time See Figure 9-5 and Figure 9-6 46 150 ns
tPZL Enable time See Figure 9-5 and Figure 9-6 36 150 ns
tPZH, tPZL Enable time See Figure 9-5 and Figure 9-6 48 110 ns
Receiver: 12-Mbps device (ISOW1432)
tr, tf Output rise time and fall time CL = 15 pF, see Figure 9-7 4 ns
tPHL Propagation delay CL = 15 pF, see Figure 9-7 59 120 ns
tPLH Propagation delay CL = 15 pF, see Figure 9-7 59 120 ns
tPHL, tPLH Propagation delay CL = 15 pF, see Figure 9-7 42 120 ns
PWD Pulse width distortion(1), |tPHL - tPLH| CL = 15 pF, see Figure 9-7 1.7 10 ns
tPHZ Disable time See Figure 9-8 and Figure 9-9 7 30 ns
tPLZ Disable time See Figure 9-8 and Figure 9-9 6 30 ns
tPHZ, tPLZ Disable time See Figure 9-8 and Figure 9-9 9 30 ns
tPZH Enable time See Figure 9-8 and Figure 9-9 6 30 ns
tPZL Enable time See Figure 9-8 and Figure 9-9 5 30 ns
tPZH, tPZL Enable time See Figure 9-8 and Figure 9-9 8 30 ns
GPIO channel
tPHL, tPLH Propagation delay time See Figure 9-11 227 347 ns
PWD Pulse width distortion, |tPHL - tPLH| 20 110 ns
tr Output signal rise time 1 4 ns
tf Output signal fall time 1 4 ns
(1) Also known as pulse skew.
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