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SLLU312A July 2019 – May 2022 TCAN4550-Q1

3.2.1.6.5 Interrupt and Internal Fault Detection

The TCAN4550-Q1 provides error detection and status notification register and interrupts to notify the host MCU of errors on internal transactions and SPI transactions, see Table 3-9. It also contains internal RAM (FIFO Buffer) ECC protection. The internal RAM is protected by ECC for single bit correction due to transient faults impacting RAM content during the read operation. See Table 3-10 and Table 3-11 for device interrupts and M_CAN specific interrupts. The Bosch M_CAN core has many other interrupt and fault tools that are provided in the data sheet.

Note:

Though these interrupts show certain failures the ones associated to safety mechanism have been included in the document above.

Table 3-9 Internal SPI Status Field Descriptions (Address h000C)

Bit	Field	Type	Reset	Description
31:30	RSVD	RO	1’b0	Reserved
29	Internal_read_error	W1C	1’b0	Internal read received an error response
28	Internal_write_error	W1C	1’b0	Internal write received an error response
27	Internal_error_log_write	W1C	1’b0	Entry written to the Internal error log
26	Read_fifo_underflow	W1C	1’b0	Read FIFO underflow after 1 or more read data words returned
25	Read_fifo_empty	W1C	1’b0	Read FIFO empty for first read data word to return
24	Write_fifo_overflow	W1C	1’b0	Write/command FIFO overflow
23:22	RSVD	RO	1’b0	Reserved
21	SPI_end_error	W1C	1’b0	SPI transfer did not end on a byte boundary
20	Invalid_command	W1C	1’b0	Invalid SPI command received
19	Write_overflow	W1C	1’b0	SPI write sequence had continue requests after the data transfer was completed
18	write_underflow	W1C	1’b0	SPI write sequence ended with less data transferred then requested
17	Read_overflow	W1C	1’b0	SPI read sequence had continue requests after the data transfer was completed
16	read_underflow	W1C	1’b0	SPI read sequence ended with less data transferred then requested
15:8	RSVD	RO	8’h00	Reserved
7:6	RSVD	RO	1’b0	Reserved
5	Write_fifo_available	RO	1’b0	write fifo empty entries is greater than or equal to the write_fifo_threshold
4	Read_fifo_available	RO	1’b0	Read fifo entries is greater than or equal to the read_fifo_threshold
3	Internal_access_active	RO	U	Internal Multiple transfer mode access in progress
2	Internal_error_interrupt	RO	1’b0	Unmasked Internal error set
1	SPI_error_interrupt	RO	1’b0	Unmasked SPI error set
0	Interrupt	RO	U	Value of interrupt input level (active high)

Table 3-10 Interrupts Field Descriptions (Address h0820)

Bit	Field	Type	Reset	Description
31	CANBUSNOM	RU	1'b0	CAN Bus normal (Flag and Not Interrupt) Changes to 1 when in Normal mode after first Dom to Rec transition
30:24	RSVD	R	7b'0000000	Reserved
23	SMS	R/WC	1'b0	Sleep Mode Status (Flag & Not an interrupt) Only sets when Sleep mode is entered by a WKERR, UVIO timeout, or UVIO+TSD fault
22	UVSUP	R/WC	1'b0	Under Voltage V_SUP and UV_CCOUT
21	UVIO	R/WC	1'b0	Under Voltage V_IO
20	PWRON	R/WC/U	1'b1	Power ON
19	TSD	R/WC	1'b0	Thermal Shutdown
18	WDTO	RU/WC	1'b0	Watchdog Time Out
17	RSVD	R	1'b0	Reserved
16	ECCERR	R/WC	1'b0	Uncorrectable ECC error detected
15	CANINT	R/WC	1'b0	Can Bus Wake Up Interrupt
14	LWU	R/WC	1'b0	Local Wake Up
13	WKERR	R/WC	1'b0	Wake Error
12	RSVD	R	1'b0	Reserved
11	RSVD	R	1'b0	Reserved
10	CANSLNT	R/WC	1'b0	CAN Silent
9	RSVD	R	1'b0	Reserved
8	CANDOM	R/WC	1'b0	CAN Stuck Dominant
7	GLOBALERR	R	1'b0	Global Error (Any Fault)
6	WKRQ	R	1'b0	Wake Request
5	CANERR	R	1'b0	CAN Error
4	RSVD	R	1'b0	RSVD
3	SPIERR	R	1'b0	SPI Error
2	RSVD	R	1'b0	Reserved
1	M_CAN_INT	R	1'b0	M_CAN global INT
0	VTWD	R	1'b0	Global Voltage, Temp or WDTO

GLOBALERR: Logical OR of all faults in registers 0x0820-0824.

WKRQ: Logical OR of CANINT, LWU and WKERR.

CANBUSNOM is not an interrupt but a flag. In Normal mode after the first dominant-recessive transition, it is set. It resets to 0 when entering Standby or Sleep modes or when a bus fault condition takes place in Normal mode.

CANERR: Logical OR of CANSLNT and CANDOM faults.

SPIERR: is set if any of the SPI status register 16'h000C[30:16] is set.

In the event of a SPI underflow, the error is not detected/alerted until the start of the next SPI transaction.
16'h0010[30:16] are the mask for these errors

VTWD: Logical or of UV_CCOUT, UVSUP, UVVIO, TSD, WDTO (Watchdog time out) and ECCERR.

CANINT: Indicates a WUP has occurred; Once a CANINT flag is set, LWU events are ignored. Flag can be cleared by changing to Normal or Sleep modes.

LWU: Indicates a local wake event, from toggling the WAKE pin, has occurred. Once a LWU flag is set, CANINT events is ignored. Flag can be cleared by changing to Normal or Sleep modes.

WKERR: If the device receives a wake up request WUP and does not transition to Normal mode or clear the PWRON or Wake flag before t_INACTIVE, the device transitions to Sleep Mode. After the wake event, a Wake Error (WKERR) is reported and the SMS flag is set to 1.

Note:

PWRON Flag is cleared by either writing a 1 or by going to Sleep mode or Normal mode from Standby mode.

Table 3-11 MCAN Interrupts Field Descriptions (Address h0824)

Bit	Field	Type	Reset	Description
31:30	RSVD	R	1'b0	Reserved
29	ARA	R	1'b0	ARA: Access to Reserved Address
28	PED	R	1'b0	PED: Protocol Error in Data Phase (Data Bit Time is used)
27	PEA	R	1’b0	PEA: Protocol Error in Arbitration Phase (Nominal Bit Time is used)
26	WDI	R	1'b0	WDI: Watchdog Interrupt
25	BO	R	1'b0	BO: Bus_Off Status
24	EW	R	1'b0	EW: Warning Status
23	EP	R	1'b0	EP: Error Passive
22	ELO	R	1'b0	ELO: Error Logging Overflow
21	BEU	R	1'b0	BEU: Bit Error Uncorrected
20	BEC	R	1'b0	BEC: Bit Error Corrected
19	DRX	R	1’b0	DRX: Message stored to Dedicated Rx Buffer
18	TOO	R	1'b0	TOO: Timeout Occurred
17	MRAF	R	1'b0	MRAF: Message RAM Access Failure
16	TSW	R	1'b0	TSW: Timestamp Wraparound
15	TEFL	R	1'b0	TEFL: Tx Event FIFO Element Lost
14	TEFF	R	1'b0	TEFF: Tx Event FIFO Full
13	TEFW	R	1'b0	TEFW: Tx Event FIFO Watermark Reached
12	TEFN	R	1'b0	TEFN: Tx Event FIFO New Entry
11	TFE	R	1’b0	TFE: Tx FIFO Empty
10	TCF	R	1'b0	TCF: Transmission Cancellation Finished
9	TC	R	1'b0	TC: Transmission Completed
8	HPM	R	1'b0	HPM: High Priority Message
7	RF1L	R	1'b0	RF1L: Rx FIFO 1 Message Lost
6	RF1F	R	1'b0	RF1F: Rx FIFO 1 Full
5	RF1W	R	1'b0	RF1W: Rx FIFO 1 Watermark Reached
4	RF1N	R	1'b0	RF1N: Rx FIFO 1 New Message
3	RF0L	R	1’b0	RF0L: Rx FIFO 0 Message Lost
2	RF0F	R	1'b0	RF0F: Rx FIFO 0 Full
1	RF0W	R	1'b0	RF0W: Rx FIFO 0 Watermark Reached
0	RF0N	R	1'b0	RF0N: Rx FIFO 0 New Message