SLLU312A July 2019 – May 2022 TCAN4550-Q1
The TCAN4550-Q1 is targeted at general-purpose automotive applications.
Examples of these types of applications include but are not limited to the applications that follow:
Figure 3-5 provides potential failure points that have diagnostic or test ability mechanisms. See Table 3-1 for each potential failure point and subsection discussing this failure point.
Potential Failure Point from Figure 3-5 | Potential Failure Point Description | Section |
---|---|---|
1 | Loss of clock input | See Section 3.2.1.2 and Section 3.2.1.3 |
2 | CAN bus | See Section 3.2.1.3, Section 3.2.1.4, Section 3.2.1.5 and Section 3.2.1.6.5 |
3 | Watchdog | See Section 3.2.1.6.2 |
4 | SPI/Processor communication | See Section 3.2.1.6.1, Section 3.2.1.2, Section 3.2.1.3, Section 3.2.1.6.2, Section 3.2.1.6.3 and Section 3.2.1.6.5 |
5 | Loss of VSUP | See Section 3.2.1.2, Section 3.2.1.3 and Section 3.2.1.6.5 |
6 | Loss of VIO | See Section 3.2.1.2, Section 3.2.1.3 and Section 3.2.1.6.5 |
7 | RST pin failure | See Section 3.2.1.6.3 and Section 3.2.1.6.4 |
8 | M_CAN Controller | See Section 3.2.1.5 and Section 3.2.1.6.5 |
9 | Loss of VCCOUT | See Section 3.2.1.3, Section 3.2.1.4 and Section 3.2.1.6.5 |
Safety-Mechanism # | Name | Description | Safety-Manual Section |
---|---|---|---|
SM-01 | Sleep Wake Error Timer (SWE) tINACTIVE | Timer used for inactivity of expected functions. Puts the device into Sleep mode | 3.2.1.2 |
SM-02 | UVSUP | VSUP undervoltage detection and Interrupt 16'h0820[22] | 3.2.1.3 |
SM-03 | UVIO | VIO undervoltage detection and Interrupt 16'h820[21] | 3.2.1.3 |
SM-04 | UVCCOUT | VCCOUT undervoltage detection and Interrupt 16'h0820[22] | 3.2.1.3 |
SM-05 | TSD | Thermal Shutdown and Interrupt 16'h0820[19] | 3.2.1.4 |
SM-06 | IOS | CAN bus short circuit current limiter | 3.2.1.5 |
SM-07 | SPI & M_CAN Test Mode | Test Mode | 3.2.1.5 |
SM-08 | SPI & M_CAN Loop Back Test Mode 1 | Test Mode | 3.2.1.5 |
SM-09 | SPI & M_CAN Loop Back Test Mode 2 | Test Mode | 3.2.1.5 |
SM-10 | CAN Transceiver Test Mode | Test Mode | 3.2.1.5 |
SM-11 | PED interrupt | Protocol Error in Data Phase; 16'h1050[28] points to 16'h1044[10:8] DLEC[2:0]; Data Phase Last Error Code | 3.2.1.5 .1 |
SM-12 | PEA interrupt | Protocol Error in Arbitration Phase; 16'h1050[27] points to 16'h1044[2:0] LEC[2:0]; Last Error Code | 3.2.1.5 .1 |
SM-13 | BEU interrupt | Bit Error Uncorrected; 16'h1050[21] Message RAM bit error detected, uncorrected | 3.2.1.5 .1 |
SM-14 | Scratchpad write/read | 3.2.1.6.1.1 | |
SM-15 | SPIERR flag | SPI error detection and Interrupt 16'h0820[3] | 3.2.1.6.1.2 |
SM-16 | M_CAN forced dominant and recessive | 3.2.1.6.1.3 | |
SM-17 | SPI and FIFO | TX and RX event FIFO | 3.2.1.6.1.4 |
SM-18 | ECC for Memory | ECCERR detection and Interrupt 16'h0820[16] | 3.2.1.6.1.5 |
SM-19 | Timeout Watchdog | WDTO detection and Interrupt 16'h0820[18] | 3.2.1.6.2 |
SM-20 | SCLK internal pull-up | Floating pins | 3.2.1.6.3 |
SM-21 | SDI internal pull-up | Floating pins | 3.2.1.6.3 |
SM-22 | nCS internal pull-up | Floating pins | 3.2.1.6.3 |
SM-23 | nWKRQ internal pull-up | Floating pins | 3.2.1.6.3 |
SM-24 | RST internal pull-down | Floating pins | 3.2.1.6.3 |
SM-25 | RST Pin | System POR reset | 3.2.1.6.4 |