SLOS265E August   1999  – March 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: THS4021
    5. 5.5 Thermal Information: THS4022
    6. 5.6 Electrical Characteristics: THS4021D and THS4022DGN
    7. 5.7 Electrical Characteristics: THS4021DGN
    8. 5.8 Typical Characteristics: THS4021D and THS4022DGN
    9. 5.9 Typical Characteristics: THS4021DGN
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 General Configuration
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
        1. 7.3.1.1 General PowerPAD™ Integrated Circuit Package Design Considerations
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.2 Functional Block Diagram

GUID-20230504-SS0I-VTR6-ML2Q-QKNB9LHFPNDX-low.svgFigure 6-1 THS4021: Single Channel
GUID-20230504-SS0I-B14N-F44F-NF8HQBWGFF40-low.svgFigure 6-2 THS4022: Dual Channel
GUID-73CBF945-E4B3-4249-B8D0-EF12DABF633A-low.gif Figure 6-3 THS4021 Simplified Schematic
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