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SLOS739A July 2012 – March 2016

PRODUCTION DATA.

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The typical connection diagram highlights the required external components and system level connections for proper operation of the device in several popular system examples.

Each of these configurations can be realized using the Evaluation Module (EVM) for the device. These flexible modules allow full evaluation of the device in the most common modes of operation. Any design variation can be supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional information.

10.2 Typical Application

Figure 71. Mono PBTL System With Headphone Driver

10.2.1 Design Requirements

Table 25 lists the design parameters of the TAS5721.

Table 25. Design Parameters

PARAMETER	EXAMPLE
Low Power Supply	3.3 V
High Power Supply	8 V to 24 V
Host Processor	I2S Compliant Master
	I2C Compliant Master
	GPIO Control
Output Filters	Inductor-Capacitor Low Pass Filter⁽¹⁾
Speaker	8 Ω minimum BTL 4 Ω minimum PBTL and Single Ended

(1) Refer to SLOA119 for a detailed description on the filter design.

10.2.2 Detailed Design Procedure

10.2.2.1 Component Selection and Hardware Connections

The typical connections required for proper operation of the device can be found on the TAS5721EVM User’s Guide (SLOU346). The device was tested this this list of components, deviation from this typical application components unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device. The application report SLOA119 offers a detailed description on proper component selection and design of the output filter based upon the modulation used, desired load and response.

10.2.2.2 I²C Pullup Resistors

Customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification.

10.2.2.3 Digital I/O Connectivity

The digital I/O lines of the TAS5721 are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count.

10.2.2.4 Recommended Startup and Shutdown Procedures

10.2.2.4.1 Recommended Use Model

Figure 72. Recommended Command Sequence

Figure 73. Power Loss Sequence

10.2.2.4.1.1 Initialization Sequence

Use the following sequence to power-up and initialize the device:

Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.
Initialize digital inputs and PVDD supply as follows:
- Drive RST = 0, PDN = 1, and other digital inputs to their desired state while ensuring that all are never more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RST = 1, and wait at least another 13.5 ms.
- Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs after AVDD/DVDD reaches 3 V. Then wait at least another 10 µs.
Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.
Configure the DAP via I²C (see Users's Guide for typical values).
Configure remaining registers.
Exit shutdown (sequence defined below).

10.2.2.4.1.2 Normal Operation

The following are the only events supported during normal operation:

Writes to master/channel volume registers.
Writes to soft mute register.
Enter and exit shutdown (sequence defined below).

NOTE

Event 3 is not supported for 240 ms + 1.3 × t_start after trim following AVDD/DVDD powerup ramp (where t_start is 300 ms when mid-Z ramp is enabled and is otherwise specified by register 0x1A).

10.2.2.4.1.3 Shutdown Sequence

Enter:

Write 0x40 to register 0x05.
Wait at least 1 ms + 1.3 × t_stop (where t_stop is specified by register 0x1A).
If desired, reconfigure by returning to step 4 of initialization sequence.

Exit:

Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms after trim following AVDD/DVDD powerup ramp).
Wait at least 1 ms + 1.3 × t_start (where t_start is 300 ms when mid-Z ramp is enabled and is otherwise specified by register 0x1A).
Proceed with normal operation.

10.2.2.4.1.4 Power-Down Sequence

Use the following sequence to powerdown the device and its supplies:

If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert PDN = 0 and wait at least 2 ms.
Assert RST = 0.
Drive digital inputs low and ramp down PVDD supply as follows:
- Drive all digital inputs low after RST has been low for at least 2 µs.
- Ramp down PVDD while ensuring that it remains above 8 V until RST has been low for at least 2 µs.
Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and that it is never more than 2.5 V below the digital inputs.