SLUAA53 October 2020 TPS628501-Q1 , TPS628502-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS62850x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to Ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to VIN (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

Figure 4-1 shows the TPS62850x-Q1 pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TPS62850x-Q1 datasheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

The device is operating in the typical application, please refer to the 'Simplified Schematics' on the 1st page in the TPS62850x-Q1 datasheet.

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
VIN	1	Device does not power up	B
EN	2	Intended functionality	D
MODE/SYNC	3	Intended functionality	D
COMP/FSET	4	Intended functionality	D
FB	5	Open loop operation and device performance degradation	C
PG	6	Intended functionality	D
SW	7	Potential device damage	A
GND	8	No effect	D

Table 4-3 Pin FMA for Device Pins Open-Circuited

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
VIN	1	Device does not power up	B
EN	2	Undetermined device operation; Device might power up or not	B
MODE/SYNC	3	Undetermined device operation	B
COMP/FSET	4	Intended functionality	D
FB	5	Device not functional; Open loop operation	B
PG	6	Intended functionality	D
SW	7	Device not functional; Open loop operation	B
GND	8	Potential device damage	A

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

Pin Name	Pin No.	Shorted to	Description of Potential Failure Effect(s)	Failure Effect Class
VIN	1	EN	Intended functionality	D
EN	2	MODE/SYNC	Intended functionality	D
MODE/SYNC	3	COMP/FSET	No device damage, but performance degradation	C
FB	5	PG	Device not functional; Open loop operation	B
PG	6	SW	Potential internal device damage	A
SW	7	GND	Potential internal device damage	A

Table 4-5 Pin FMA for Device Pins Short-Circuited to VIN

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
VIN	1	Intended functionality	D
EN	2	Intended functionality; Device enabled	D
MODE/SYNC	3	Intended functionality; FPWM mode	D
COMP/FSET	4	Intended functionality; Device operation in fix frequency	D
FB	5	Device not functional; Open loop operation	B
PG	6	Potential device damage	A
SW	7	Potential device damge	A
GND	8	Device not functional	B