4 Input Under Voltage Lockout (UVLO) Protection

These flyback controllers have programmable input under voltage detection that can be set and adjusted primary to auxiliary turns ration and properly selecting R_S1 and R_S2Figure 1-1. Refer to the flyback controller data sheet for instructions on programming the input UVLO.

The VS pin of these flyback controllers have an internal clamp on the VS pin that clamps the VS pin to roughly ground (GND) while Q1 is on (t_ON), (Figure 3-1 and Figure 3-2). During this this time the current coming out of the VS pin (I_VSL) in combination with R_S1 and the N_P/N_A turns ratio will determine the input voltage level the flyback converter will start at (V_IN(run)) and what input voltage the converter will stop switching at (V_IN(stop)). The value I_VSL(run) start and I_VSL(stop) stop thresholds will vary based on the flyback controller that is used in the design, refer to the flyback controller data sheet for the correct values.

The design presented in Figure 1-1 does not start switching until V_IN is greater than 67 V and will stop switching when V_IN drops below 23.8 V. Refer to Equation 3 through Equation 6 for details.

When power is first applied to V_IN the VDD capacitor (C_DD) trickle charges through R_T of Figure 1-1. Note that some flyback controllers trickle charge the C_DD capacitor with an internal JFET startup circuit. The capacitor continues to trickle charge until the flyback controllers turn on threshold is reached (V_VDD(on)). At this point it will deliver 3 gate drivers pulse to sample V_IN and V_OUT at the controllers maximum switching frequency (f_SW(max)). The UCC28704 controls the primary current to I_PP(max) /4. At this point t_{LK_RESET} will be reduced to it's minimum blanking time of 750 ns. If the converter detects a UVLO and/or a OVP fault during this time, the gate driver stops switching and the I_DD current will discharge C_DD to the flyback controllers turnoff threshold (V_VDD(off)). After C_DD is discharged to V_VDD(off), C_DD will once again be charged through R_T until the VDD pin reaches V_VDD(on). At this point the controller will sample V_OUT and V_IN again. If the fault is cleared the flyback will continue to operate. If the fault is not cleared switching will stop and the C_DD capacitor will be discharged and charged between V_VDD(off) and V_VDD(on) until the fault is cleared.

Figure 4-1, shows an example of how the input fault protection operates with different input voltages. At the beginning of time interval t_A 50 V is applied at V_IN, the C_DD capacitor trickle charged up to V_VDD(on). The flyback controller samples the input through N_P/N_A turns ratio and will detect an input UVLO fault and stops switching. The controller enters fault mode operation during this time interval. At the beginning of time interval t_B the input voltage is increase to 120 V, however, the flyback controller is still not switching, it waits until C_DD is charge up to V_VDD(on) to gives three DRV pulses to sample the input voltage. At the beginning of time internal t_C the flyback controller based on input sampling is no longer in a UVLO condition and the flyback converter will continue switching. The C_DD capacitor will discharge down to the reflected output voltage determined by the N_A/N_S turns ratio, at this point the flyback controller will be powered by the auxiliary winding (N_A) of T1. At the beginning of time interval t_D the input voltage was removed from V_IN simulating a brown out condition. The input bulk capacitor C_IN discharges based on the loading on the output of the flyback converter. At the beginning of time interval t_E capacitor C_IN will have discharged to a point where the input voltage will cause a UVLO fault. The UVLO fault has to be sampled in three consecutive switching cycles before the flyback controller stop switching. The flyback controller will remain operating in this mode until an input voltage is applied to V_IN that causes the I_VLS current to be greater than I_VSL(run).

Figure 4-1 Example of UVLO Fault Detection