SLUAAF1 May 2021 TPS62933
Small outline transistor (SOT) packages are widely used due to their low cost and low profile, the SOT23 is one of the most widely used SOT packages. But today more DC/DCs are using the SOT5x3 packages, whose size is even smaller than that of the SOT23 package. Due to the limit size, bonding wire technology is not recommended to use in SOT5x3 package and thus it does not have a thermal PAD. As a result, improving the thermal performance for chips with SOT5x3 package both in the IC design phase and the PCB layout design phase is necessary.
Bonding wire and FCOL have different ways to connect the die with the package. This paper shows the differences between two bump methods, and introduces a general rule for SOT5x3 package layout and gives an example of TI suggested layout. Finally, based on the layout analysis, this paper compares the thermal performance of FCOL SOT5x3 package with FCOL SOT23 package and bonding wore SO Power PAD package.