SLUAAG2 October 2021 UCC28782

5 Transformer design

ACF is designed for high switching frequency application, so there are several item also need to be careful during the transformer design, and these suggestion is based on 60W PD design.

Using Litz wire for bobbin design

The ACF is designed for high switching frequency application, and its switching frequency may up to 500KHz during the ABM, so the skin effect will cause lots of ACR loss, the suggested primary side winding is 20*0.05mm, and secondary side winding is 150*0.05mm. Aux-winding DCR need to less than 0.1Ω.

Core material

Same as previous mention that switching may up to 500KHz, so Core material suggest optimized with 300KHz~500KHz range to reduce the core loss, and there are some suggested core material as below list. The Bmax also suggest to within 0.2T to reduce the core loss.

TDK-N49; Ferroxcube-3F36; Hitachi-ML90S

Turn ratio

The turn ratio is limited by primary side MOS and SR MOS voltage rating, turn ratio within 5~6 is suggested for 20V PD application.

Maximum turn ratio (N_PS(MAX)) is limited by the maximum derated drain-to-source voltage of low side MOS (V_{DS_QL(MAX)}). In the expression below, ∆V_CLAMP is a voltage deviation above the reflected output voltage. It can be either the ripple voltage of C_CLAMP in AAM mode, or the voltage over-charge of C_CLAMP by the leakage inductance energy when high side MOS is disabled in LPM. V_O is the output voltage, and VF is the forward voltage drop of the secondary rectifier.

Equation 7.

N_{P S (M A X)} = \frac{V_{D S_Q L (M A X)} - V_{B U L K (M A X)} - {∆ V}_{C L A M P}}{V_{O} + V_{F}}

Minimum turn ratio (N_PS(MIN)) is limited by the maximum derated drain-to-source voltage of the secondary rectifier (V_{DS_SR(MAX)}). In the expression for N_PS(MIN), ∆VSPIKE should account for any additional voltage spike higher than V_BULK(MAX)/NPS that occurs when high side MOS is active and turns-off at non-zero current in AAM mode.

Equation 8.

N_{P S (M I N)} = \frac{V_{B U L K (M A X)}}{V_{D S_S R (M A X)} - V_{O} - {∆ V}_{S P I K E}}

Inductance

Lm can be estimated based on minimum switching frequency (F_SW(MIN)) at V_BULK(MIN), maximum duty cycle (D_MAX), and output power at highest nominal output voltage, nominal full-load current (P_O(FL)).

Lr is suggested within 3uH to reduce the VDS spike during LPM.

Equation 9.

D_{M A X} = \frac{N_{P S} (V_{O} + V_{F})}{V_{B U L K (M I N)} + N_{P S} (V_{O} + V_{F})}

Equation 10.

L_{M} = \frac{D_{M A X}^{2} V_{B U L K (M I N)}^{2} η}{{2 P}_{O (F L)}} \times \frac{(1 - K_{R E S})}{F_{S W (M I N)}}