5 Sequencing VDD_CORE and VDDR_CORE Rails

When VDD_CORE is supplied at 0.75 V instead of 0.85 V, power on or off sequencing between the VDD_CORE and VDDR_CORE rails become important. The sequencing requirement of ramping up the VDD_CORE rail before the VDDR_CORE rail during power on and ramping down after the VDDR_CORE rail during power off is achieved by using simple AND and OR gates along with an RC delay.

During power on, a logic high on the PG pin of the 1.2 V VDDS_DDR rail enables the VDD_CORE rail. Since the PG of the VDD_CORE rail is also an input to the AND gate driving the EN pin of VDDR_CORE rail, the VDDR_CORE rail will only get enabled after the VDD_CORE rail completes its startup. For the power down sequence, a logic low on the PG pin of the 1.2 V VDDS_DDR rail disables the VDDR_CORE rail. Once the VDDR_CORE rail starts discharging its output, a logic low on the PG pin will cause the output of the OR gate driving the EN pin of the VDD_CORE rail through the RC filter to go low. However, the RC filter adds a delay to the output of the OR gate, thereby delaying the turn off of the VDD_CORE rail.

Figure 5-1 and Figure 5-2 show the power on and off sequencing achieved between the VDD_CORE and VDDR_CORE on the AM62x discrete power EVM. On this EVM, the VDDR_ CORE was configured to run at 0.85 V. The logic for the required sequencing when the VDD_CORE rail runs at 0.75 V was implemented on this EVM to demonstrate functionality. The value of the RC delay depends on the value of the output discharge resistor or current sink of the converters supplying these rails. For the recommended TPS6282x regulators, an RC delay of 0.1 ms made up with a 1 KOhm and a 0.1 µF capacitor is sufficient.