SLUS772G March 2008 – June 2020 TPS40210 , TPS40211
PRODUCTION DATA
The TPS40210 drives a ground referenced N-channel FET. The RDS(on) and gate charge are estimated based on the desired efficiency target.
For a target of 95% efficiency with a 24-V input voltage at 2 A, maximum power dissipation is limited to 2.526 W. The main power dissipating devices are the MOSFET, inductor, diode, current sense resistor and the integrated circuit, the TPS40210.
This leaves 812 mW of power dissipation for the MOSFET. This can likely cause an SO-8 MOSFET to get too hot, so power dissipation is limited to 500 mW. Allowing half for conduction and half for switching losses, we can determine a target RDS(on) and QGS for the MOSFET by Equation 55 and Equation 56.
A target MOSFET gate-to-source charge of less than 13.0 nC is calculated to limit the switching losses to less than 250 mW.
A target MOSFET RDS(on) of 9.9 mΩ is calculated to limit the conduction losses to less than 250 mW. Reviewing 30-V and 40-V MOSFETs, an Si4386DY 9-mΩ MOSFET is selected. A gate resistor was added per Equation 30. The maximum gate charge at VGS= 8V for the Si4386DY is 33.2 nC, this implies RG = 3.3 Ω.