SLUS828D December   2008  – October 2017 UCC28019A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Soft-Start
      2. 7.3.2  System Protection
        1. 7.3.2.1  VCC Undervoltage Lockout (UVLO)
        2. 7.3.2.2  Input Brown-Out Protection (IBOP)
        3. 7.3.2.3  Output Overvoltage Protection (OVP)
        4. 7.3.2.4  Open Loop Protection/Standby (OLP/Standby)
        5. 7.3.2.5  ISENSE Open-Pin Protection (ISOP)
        6. 7.3.2.6  Output Undervoltage Detection (UVD) and Enhanced Dynamic Response (EDR)
        7. 7.3.2.7  Over-Current Protection
        8. 7.3.2.8  Soft Over Current (SOC)
        9. 7.3.2.9  Peak Current Limit (PCL)
        10. 7.3.2.10 Current Sense Resistor, RISENSE
      3. 7.3.3  Gate Driver
      4. 7.3.4  Current Loop
      5. 7.3.5  ISENSE and ICOMP Functions
      6. 7.3.6  Pulse Width Modulator
      7. 7.3.7  Control Logic
      8. 7.3.8  Voltage Loop
      9. 7.3.9  Output Sensing
      10. 7.3.10 Voltage Error Amplifier
      11. 7.3.11 Non-Linear Gain Generation
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Current Calculations
        2. 8.2.2.2  Bridge Rectifier
        3. 8.2.2.3  Input Capacitor
        4. 8.2.2.4  Boost Inductor
        5. 8.2.2.5  Boost Diode
        6. 8.2.2.6  Switching Element
        7. 8.2.2.7  Sense Resistor
        8. 8.2.2.8  Output Capacitor
        9. 8.2.2.9  Output Voltage Set Point
        10. 8.2.2.10 Loop Compensation
        11. 8.2.2.11 Brown Out Protection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Bias Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Related Products
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The UCC28019A is a switch-mode controller used in boost converters for power factor correction operating at a fixed frequency in continuous conduction mode. The UCC28019A requires few external components to operate as an active PFC pre-regulator. The operating switching frequency is fixed at 65 kHz.

The internal 5-V reference voltage provides for accurate output voltage regulation over the typical world-wide 85-VAC to 265-VAC mains input range from zero to full output load. The usable system load ranges from 100 W to few kW.

Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the sinusoidal input voltage under continuous inductor current conditions. Under light-load conditions, depending on the boost inductor value, the inductor current may go discontinuous but still meet Class-A/D requirements of IEC 61000-3-2 despite the higher harmonics. The outer voltage loop regulates the PFC output voltage by generating a voltage on VCOMP (dependent upon the line and load conditions) which determines the internal gain parameters for maintaining a low-distortion, steady-state, input-current wave shape.

Typical Application

Figure 26 illustrates the design process and component selection for a continuous conduction mode power factor correction boost converter utilizing the UCC28019A. The target design is a universal input, 350-W PFC designed for an ATX supply application. This design process is directly tied to the UCC28019A Design Calculator (SLUC117) spreadsheet that can be found in the Tools section of the UCC28019A product folder on the Texas Instruments website.

UCC28019A defig1_lus828.gif Figure 26. Design Example Schematic

Design Requirements

Design goal parameters for a continuous conduction mode power factor correction boost converter utilizing the UCC28019A.

Table 1. Design Goal Parameters

PARAMETER TEST CONDITION MIN TYP MAX UNIT
Input characteristics
VIN Input voltage 85 115 265 VAC
fLINE Input frequency 47 63 Hz
Brown out voltage VAC(on), IOUT = 0.9 A 75 VAC
VAC(off), IOUT = 0.9 A 65 VAC
Output characteristics
VOUT Output voltage 85 VAC ≤ VIN ≤ 265 VAC, 47 Hz ≤ fLINE ≤ 63 Hz
0 A ≤ IOUT ≤ 0.9 A
380 390 402 VDC
VRIPPLE(SW) High frequency output voltage ripple VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A 3.9 VPP
VIN = 230 VAC , fLINE = 50 Hz, IOUT = 0.9 A 3.9 VPP
VRIPPLE(f_LINE) Line frequency output voltage ripple VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A 19.5 VPP
VIN = 230 VAC, fLINE = 50 Hz, IOUT = 0.9 A 19.5 VPP
IOUT Output load current 85 VAC ≤ VIN ≤ 265 VAC, 47 Hz ≤ fLINE ≤ 63 Hz 0.9 A
POUT Output power 350 W
VOUT(OVP) Output over voltage protection 410 V
VOUT(UVP) Output under voltage protection 370 V
Control loop characteristics
fSW Switching frequency TJ = 25°C 61.7 65 68.3 kHz
f(CO) Control loop bandwidth VIN = 162 VDC, IOUT = 0.45 A 14 Hz
Phase margin VIN = 162 VDC, IOUT = 0.45 A 70 degrees
PF Power factor VIN = 115 VAC, IOUT = 0.9 A 0.98
THD Total harmonic distortion VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A 4.3% 10%
VIN = 230 VAC, fLINE = 50 Hz, IOUT = 0.9 A 6.6% 10%
η Full load efficiency VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A 0.95
TAMB Ambient temperature 50 °C

Detailed Design Procedure

Current Calculations

First, determine the maximum average output current, IOUT(max):

Equation 8. UCC28019A qu1de_lus828.gif
Equation 9. UCC28019A qu2de_lus828.gif

The maximum input RMS line current, IIN_RMS(max), is calculated using the parameters from Table 1 and the efficiency and power factor initial assumptions:

Equation 10. UCC28019A qu3de_lus828.gif
Equation 11. UCC28019A qu4de_lus828.gif

Based upon the calculated RMS value, the maximum peak input current, IIN_PEAK(max), and the maximum average input current, IIN_AVG(max), assuming the waveform is sinusoidal, can be determined.

Equation 12. UCC28019A qu5de_lus828.gif
Equation 13. UCC28019A qu6de_lus828.gif
Equation 14. UCC28019A qu7de_lus828.gif
Equation 15. UCC28019A qu8de_lus828.gif

Bridge Rectifier

Assuming a forward voltage drop, VF_BRIDGE, of 0.95 V across the rectifier diodes, BR1, the power loss in the input bridge, PBRIDGE, can be calculated:

Equation 16. UCC28019A qu9de_lus828.gif
Equation 17. UCC28019A qu10de_lus828.gif

Input Capacitor

Note that the UCC28019A is a continuous conduction mode controller and as such the inductor ripple current should be sized accordingly. High inductor ripple current has an impact on the CCM/DCM boundary and results in higher light-load THD, and also affects the choices for RSENSE and CICOMP values. Allowing an inductor ripple current, IRIPPLE, of 20% and a high frequency ripple voltage factor, ΔVRIPPLE_IN, of 6%, the minimum input capacitor value, CIN, is calculated by first determining the input ripple current, IRIPPLE, and the input ripple voltage, VIN_RIPPLE(max):

Equation 18. UCC28019A qu11de_lus828.gif
Equation 19. UCC28019A qu12de_lus828.gif
Equation 20. UCC28019A qu13de_lus828.gif
Equation 21. UCC28019A qu14de_lus828.gif
Equation 22. UCC28019A qu15de_lus828.gif
Equation 23. UCC28019A qu16de_lus828.gif
Equation 24. UCC28019A qu17de_lus828.gif
Equation 25. UCC28019A qu18de_lus828.gif

The value for the input x-capacitor can now be calculated:

Equation 26. UCC28019A qu19de_lus828.gif
Equation 27. UCC28019A qu20de_lus828.gif

A 0.33 μF, 275 VAC ex-2 film capacitor was selected for CIN.

Boost Inductor

The boost inductor, LBST, is selected after determining the maximum inductor peak current, IL_PEAK(max):

Equation 28. UCC28019A qu21de_lus828.gif
Equation 29. UCC28019A qu22de_lus828.gif

The minimum value of the boost inductor is calculated based upon a worst case duty cycle of 0.5:

Equation 30. UCC28019A qu23de_lus828.gif
Equation 31. UCC28019A qu24de_lus828.gif

The actual value of the boost inductor that will be used is 1.25 mH.

The maximum duty cycle, DUTY(max), can be calculated and will occur at the minimum input voltage:

Equation 32. UCC28019A qu25de_lus828.gif
Equation 33. UCC28019A qu26de_lus828.gif
Equation 34. UCC28019A qu27de_lus828.gif

Boost Diode

The diode losses are estimated based upon the forward voltage drop, VF, at 125°C and the reverse recovery charge, QRR, of the diode. This design uses a silicon-carbide diode. Although somewhat more expensive, it essentially eliminates the reverse recovery losses because QRR is equal to 0nC.

Equation 35. UCC28019A qu28de_lus828.gif
Equation 36. UCC28019A qu29de_lus828.gif
Equation 37. UCC28019A qu30de_lus828.gif
Equation 38. UCC28019A qu31de_lus828.gif

Switching Element

The conduction losses of the switch are estimated using the RDS(on) of the FET at 125°C , found in the FET data sheet, and the calculated drain to source RMS current, IDS_RMS:

Equation 39. UCC28019A qu32de_lus828.gif
Equation 40. UCC28019A qu33de_lus828.gif
Equation 41. UCC28019A qu34de_lus828.gif
Equation 42. UCC28019A qu35de_lus828.gif
Equation 43. UCC28019A qu36de_lus828.gif

The switching losses are estimated using the rise time, (tr), and fall time, (tf), of the gate, and the output capacitance losses.

For the selected device:

Equation 44. UCC28019A qu37de_lus828.gif
Equation 45. UCC28019A qu38de_lus828.gif
Equation 46. UCC28019A qu39de_lus828.gif
Equation 47. UCC28019A qu40de_lus828.gif

Total FET losses:

Equation 48. UCC28019A qu41de_lus828.gif

Sense Resistor

To accommodate the gain of the internal non-linear power limit, RSENSE is sized such that it will trigger the soft over-current at 25% higher than the maximum peak inductor current using the minimum SOC threshold, VSOC, of ISENSE.

Equation 49. UCC28019A qu42de_lus828.gif
Equation 50. UCC28019A qu43de_lus828.gif

Using a parallel combination of available standard value resistors, the sense resistor is chosen.

Equation 51. UCC28019A qu44de_lus828.gif

The power dissipated across the sense resistor, PRsense, must be calculated:

Equation 52. UCC28019A qu45de_lus828.gif
Equation 53. UCC28019A qu46de_lus828.gif

The peak current limit, PCL, protection feature will be triggered when current through the sense resistor results in the voltage across RSENSE to be equal to the VPCL threshold. For a worst case analysis, the maximum VPCL threshold is used:

Equation 54. UCC28019A qu47de_lus828.gif
Equation 55. UCC28019A qu48de_lus828.gif

To protect the device from inrush current, a standard 220-Ω resistor, RISENSE, is placed in series with the ISENSE pin. A 1000-pF capacitor, CISENSE, is placed close to the device to improve noise immunity on the ISENSE pin.

Output Capacitor

The output capacitor, COUT, is sized to meet holdup requirements of the converter. Assuming the downstream converters require the output of the PFC stage to never fall below 300 V, VOUT_HOLDUP(min), during one line cycle, tHOLDUP = 1/fLINE(min), the minimum calculated value for the capacitor is:

Equation 56. UCC28019A qu49de_lus828.gif
Equation 57. UCC28019A qu50de_lus828.gif

It is advisable to de-rate this capacitor value by 20%; the actual capacitor used is 270 μF.

Setting the maximum peak-to-peak output ripple voltage to be less than 5% of the output voltage will ensure that the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the controller. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple current of the output capacitor are calculated:

Equation 58. UCC28019A qu51de_lus828.gif
Equation 59. UCC28019A qu52de_lus828.gif
Equation 60. UCC28019A qu53de_lus828.gif
Equation 61. UCC28019A qu54de_lus828.gif

The required ripple current rating at twice the line frequency is equal to:

Equation 62. UCC28019A qu55de_lus828.gif
Equation 63. UCC28019A qu56de_lus828.gif

There will also be a high frequency ripple current through the output capacitor:

Equation 64. UCC28019A qu57de_lus828.gif
Equation 65. UCC28019A qu58de_lus828.gif

The total ripple current in the output capacitor is the combination of both and the output capacitor must be selected accordingly:

Equation 66. UCC28019A qu59de_lus828.gif
Equation 67. UCC28019A qu60de_lus828.gif

Output Voltage Set Point

For low power dissipation and minimal contribution to the voltage set point error, it is recommended to use 1 MΩ for the top voltage feedback divider resistor, RFB1. Multiple resistors in series are used due to the maximum allowable voltage across each. Using the internal 5-V reference, VREF, select the bottom divider resistor, RFB2, to meet the output voltage design goals.

Equation 68. UCC28019A qu61de_lus828.gif
Equation 69. UCC28019A qu62de_lus828.gif

Using 13 kΩ for RFB2 results in a nominal output voltage set point of 391 V.

The over-voltage protection, OVD, will be triggered when the output voltage exceeds 5% of its nominal set-point:

Equation 70. UCC28019A qu63de_lus828.gif
Equation 71. UCC28019A qu64de_lus828.gif

The under-voltage detection, UVD, will be triggered when the output voltage falls below 5% of its nominal set-point:

Equation 72. UCC28019A qu65de_lus828.gif
Equation 73. UCC28019A qu66de_lus828.gif

A small capacitor on VSENSE must be added to filter out noise. Limit the value of the filter capacitor such that the RC time constant is less than 0.1 ms so as not to significantly reduce the control response time to output voltage deviations. With careful layout, the noise on this design is minimal, so an RC time constant of 0.01 ms was all that was needed:

Equation 74. UCC28019A qu1p32de_lus828.gif
Equation 75. UCC28019A qu2p32de_lus828.gif

Loop Compensation

The selection of compensation components, for both the current loop and the voltage loop, is made easier by using the UCC28019A Design Calculator spreadsheet that can be found in the Tools section of the UCC28019A product folder on the Texas Instruments website. The current loop is compensated first by determining the product of the internal loop variables, M1M2, using the internal controller constants K1 and KFQ:

Equation 76. UCC28019A qu67de_lus828.gif
Equation 77. UCC28019A qu68de_lus828.gif
Equation 78. UCC28019A qu69de_lus828.gif
Equation 79. UCC28019A qu70de_lus828.gif
Equation 80. UCC28019A qu71de_lus828.gif

The VCOMP operating point is found on Figure 27. The Design Calculator spreadsheet enables the user to iteratively select the appropriate VCOMP value.

UCC28019A defig2_lus828.gif Figure 27. M1M2 vs. VCOMP

For the given M1M2 of 0.374 V/μs, the VCOMP is approximately equal to 4, as shown in Figure 27.

The individual loop factors, M1 which is the current loop gain factor, and M2 which is the voltage loop PWM ramp slope, are calculated using the following conditions:

The M1 current loop gain factor:

  • if : 0 < VCOMP < 2
Equation 81. UCC28019A qu72de_lus828.gif
  • if : 2 ≤ VCOMP < 3
Equation 82. UCC28019A qu73de_lus828.gif
  • if : 3 ≤ VCOMP < 5.5
Equation 83. UCC28019A qu74de_lus828.gif
  • if : 5.5 ≤ VCOMP < 7
Equation 84. UCC28019A qu75de_lus828.gif

In this example:

Equation 85. UCC28019A qu76de_lus828.gif

The M2 PWM ramp slope:

  • if : 0 < VCOMP < 1.5
Equation 86. UCC28019A qu77de_lus828.gif
  • if : 1.5 ≤ VCOMP < 5.6
Equation 87. UCC28019A qu78de_lus828.gif
  • if : 5.6 ≤ VCOMP < 7
Equation 88. UCC28019A qu79de_lus828.gif

In this example:

Equation 89. UCC28019A qu80de_lus828.gif

Verify that the product of the individual gain factors is approximately equal to the M1M2 factor determined above, if not, reselect VCOMP and recalculate M1M2.

Equation 90. UCC28019A qu81de_lus828.gif
Equation 91. UCC28019A qu82de_lus828.gif

The non-linear gain variable, M3, can now be calculated:

  • if : 0 < VCOMP < 3
Equation 92. UCC28019A qu83de_lus828.gif
  • if : 3 ≤ VCOMP < 7
Equation 93. UCC28019A qu84de_lus828.gif

In this example:

Equation 94. UCC28019A qu85de_lus828.gif

The frequency of the current averaging pole, fIAVG, is chosen to be at 9.5 kHz. The required capacitor on ICOMP, CICOMP, for this is determined using the transconductance gain, gmi, of the internal current amplifier:

Equation 95. UCC28019A qu86de_lus828.gif
Equation 96. UCC28019A qu87de_lus828.gif

Using a 1200 pF capacitor for CICOMP results in a current averaging pole frequency of 8.7 kHz:

Equation 97. UCC28019A qu1p35de_lus828.gif
Equation 98. UCC28019A qu2p35de_lus828.gif

The transfer function of the current loop can be plotted:

Equation 99. UCC28019A qu88de_lus828.gif
Equation 100. UCC28019A qu89de_lus828.gif
UCC28019A defig3_lus828.gif Figure 28. Bode Plot of the Current Averaging Circuit.

The open loop of the voltage transfer function, GVL(f) contains the product of the voltage feedback gain, GFB, and the gain from the pulse width modulator to the power stage, GPWM_PS, which includes the pulse width modulator to power stage pole, fPWM_PS. The plotted result is shown in Figure 29.

Equation 101. UCC28019A qu90de_lus828.gif
Equation 102. UCC28019A qu91de_lus828.gif
Equation 103. UCC28019A qu92de_lus828.gif
Equation 104. UCC28019A qu93de_lus828.gif
Equation 105. UCC28019A qu94de_lus828.gif
Equation 106. UCC28019A qu95de_lus828.gif
Equation 107. UCC28019A qu96de_lus828.gif
UCC28019A newdefig4_lus828.gif Figure 29. Bode Plot of the Open Loop Voltage Transfer Function

The voltage error amplifier is compensated with a zero, fZERO, at the fPWM_PS pole and a pole, fPOLE, placed at 20 Hz to reject high frequency noise and roll off the gain amplitude. The overall voltage loop crossover, fV, is desired to be at 10 Hz. The compensation components of the voltage error amplifier are selected accordingly.

Equation 108. UCC28019A qu97de_lus828.gif
Equation 109. UCC28019A qu98de_lus828.gif
Equation 110. UCC28019A qu99de_lus828.gif
Equation 111. UCC28019A qu100de_lus828.gif

From Figure 29, and the Design Calculator spreadsheet, the open loop gain of the voltage transfer function at 10 Hz is approximately 0.667 dB. Estimating that the parallel capacitor, CVCOMP_P, is much smaller than the series capacitor, CVCOMP, the unity gain will be at fV, and the zero will be at fPWM_PS, the series compensation capacitor is determined:

Equation 112. UCC28019A qu101de_lus828.gif
Equation 113. UCC28019A qu102de_lus828.gif

A 3.3-μF capacitor is used for CVCOMP.

Equation 114. UCC28019A qu103de_lus828.gif
Equation 115. UCC28019A qu104de_lus828.gif

A 33.2-kΩ resistor is used for RVCOMP.

Equation 116. UCC28019A qu105de_lus828.gif
Equation 117. UCC28019A qu106de_lus828.gif

A 0.22-μF capacitor is used for CVCOMP_P.

The total closed loop transfer function, GVL_total, contains the combined stages and is plotted in Figure 30.

Equation 118. UCC28019A qu107de_lus828.gif
Equation 119. UCC28019A qu108de_lus828.gif
UCC28019A newdefig5_lus828.gif Figure 30. Closed Loop Voltage Bode Plot

Brown Out Protection

Select the top divider resistor into the VINS pin so as not to contribute excessive power loss. The extremely low bias current into VINS means the value of RVINS1 could be hundreds of megaOhms. For practical purposes, a value less than 10 MΩ is usually chosen. Assuming approximately 150 times the input bias current through the resistor dividers will result in an RVINS1 that is less than 10 MΩ , so as to not contribute excessive noise, and still maintain minimal power loss. The brown out protection will turn off the gate drive when the input falls below the user programmable minimum voltage, VAC(off), and turn on when the input rises above VAC(on).

Equation 120. UCC28019A qu1bo_lus828.gif
Equation 121. UCC28019A qu2bo_lus828.gif
Equation 122. UCC28019A qu3bo_lus828.gif
Equation 123. UCC28019A qu4bo_lus828.gif
Equation 124. UCC28019A qu5bo_lus828.gif
Equation 125. UCC28019A qu6bo_lus828.gif

A 6.5-M resistance is chosen.

Equation 126. UCC28019A qu7bo_lus828.gif
Equation 127. UCC28019A qu8bo_lus828.gif

The capacitor on VINS, CVINS, is selected so that it's discharge time is greater than the output capacitor hold up time. COUT was chosen to meet one-cycle hold-up time so CVINS will be chosen to meet 2.5 half-line cycles.

Equation 128. UCC28019A qu9bo_lus828.gif
Equation 129. UCC28019A qu10bo_lus828.gif
Equation 130. UCC28019A qu11bo_lus828.gif
Equation 131. UCC28019A qu12bo_lus828.gif

Application Curves

UCC28019A D011_SLUS828.gif Figure 31. Power Factor vs. Load Current
UCC28019A D012_SLUS828.gif Figure 32. Total Harmonic Distortion vs. Load Current