SLUSAM9E July 2011 – April 2020
PRODUCTION DATA.
The Host writes to the registers of the BQ76925 device as shown in Figure 13. The BQ76925 acknowledges each received byte by pulling the SDA line low during the acknowledge period.
The Host may optionally send a CRC after the Data byte as shown. The CRC for write commands is enabled by writing the CRC_EN bit in the CONFIG_2 register. If the CRC is not used, then the Host generates the Stop condition immediately after the BQ76925 acknowledges receipt of the Data byte.
When the CRC is disabled, the BQ76925 device will act on the command on the first rising edge of SCL following the ACK of the Data byte. This occurs as part of the normal bus setup prior to a Stop. If a CRC byte is sent while the CRC is disabled, the first rising edge of the SCL following the ACK will be the clocking of the first bit of the CRC. The BQ76925 device does not distinguish these two cases. In both cases, the command will complete normally, and in the latter case the CRC will be ignored.