SLUSCK0G November   2017  – November 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Thermal Derating Curves
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Minimum Pulses
    2. 7.2 Propagation Delay and Pulse Width Distortion
    3. 7.3 Rising and Falling Time
    4. 7.4 Input and Disable Response Time
    5. 7.5 Power-up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21220 and UCC21220A
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimating Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

6.8 Electrical Characteristics

VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1uF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, unless otherwise noted(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCCI VCCI quiescent current VINA = 0 V, VINB = 0 V 1.4 2.0 mA
IVDDA, IVDDB VDDA and VDDB quiescent current VINA = 0 V, VINB = 0 V 1.2 2.0 mA
IVCCI VCCI operating current (f = 500 kHz) current per channel 2.7 3.2 mA
IVDDA, IVDDB VDDA and VDDB operating current (f = 500 kHz) current per channel, VVDDA, VVDDB = 12 V 2.7 4.4 mA
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ON UVLO Rising threshold 2.55 2.7 2.85 V
VVCCI_OFF UVLO Falling threshold 2.35 2.5 2.65 V
VVCCI_HYS UVLO Threshold hysteresis 0.2 V
UCC21220A VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS (5-V UVLO Version)
VVDDA_ON, VVDDB_ON UVLO Rising threshold 5.7 6.0 6.3 V
VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 5.4 5.7 6.0 V
VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 0.3 V
UCC21220 VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS (8-V UVLO Version)
VVDDA_ON, VVDDB_ON UVLO Rising threshold 7.7 8.5 8.9 V
VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 7.2 7.9 8.4 V
VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 0.6 V
INA, INB AND DISABLE
VINAH, VINBH, VDISH Input high threshold voltage 2 2.3 V
VINAL, VINBL, VDISL Input low threshold voltage 0.8 1 V
VINA_HYS, VINB_HYS, VDIS_HYS Input threshold hysteresis 1 V
OUTPUT
IOA+, IOB+ Peak output source current CVDD = 10 µF, CLOAD = 0.22 µF, f = 1 kHz, bench measurement -4 A
IOA-, IOB- Peak output sink current CVDD = 10 µF, CLOAD = 0.22 µF, f = 1 kHz, bench measurement 6 A
ROHA, ROHB Output resistance at high state IOUT = –5 mA, ROHA, ROHB do not represent drive pull-up performance. See tRISE in Section 6.9 and Section 8.3.4 for more details. 5 Ω
ROLA, ROLB Output resistance at low state IOUT = 5 mA 0.55 Ω
VOAPDA, VOAPDB Driver output (VOUTA, VOUTB) active pull down VVDDA and VVDDB unpowered, IOUTA, IOUTB = 200 mA 1.6 2 V
(1) Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless otherwise noted).
(2) Parameters that has only typical values, are not production tested and guaranteed by design.
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