Figure 6-1 and Figure 8-6 shows the bench test waveforms for the design example shown in Figure 8-1 under these conditions: VCC = 5 V, VDD = 20 V, f_SW = 100 kHz, V_DC-Link = 0 V.

Channel 1 (Yellow): UCC21520-Q1 INA pin signal.

Channel 2 (Blue): UCC21520-Q1 INB pin signal.

Channel 3 (Pink): Gate-source signal on the high side power transistor.

Channel 4 (Green): Gate-source signal on the low side power transistor.

In Figure 8-5, INA and INB are sent complimentary 3.3-V, 50% duty-cycle signals. The gate drive signals on the power transistor have a 250-ns dead time, shown in the measurement section of Figure 8-5. The dead-time matching is less than 1 ns with the 250-ns dead-time setting.

Figure 8-6 shows a zoomed-in version of the waveform of Figure 8-5, with measurements for propagation delay and rising/falling time. Cursors are also used to measure dead time. Importantly, the output waveform is measured between the power transistors’ gate and source pins, and is not measured directly from the driver OUTA and OUTB pins. Due to the split on and off resistors (R_on,R_off) and different sink and source currents, different rising (16 ns) and falling time (9 ns) are observed in Figure 8-6.

Figure 8-5 Bench Test Waveform for INA/B and OUTA/B

Figure 8-6 Zoomed-In Bench Test Waveform