Low-ESR and low-ESL capacitors must be
connected close to the device between the VCCI and GND pins and between the VDD and VSS
pins to support high peak currents when turning on the external power transistor.
To avoid large negative transients on the
switch node VSSA (HS) pin in bridge configurations, the parasitic inductances between the
source of the top transistor and the source of the bottom transistor must be
minimized.
To improve noise immunity when driving
the EN pin from a distant micro-controller, TI recommends adding a small bypass capacitor,
≥ 1 nF, between the EN pin and GND.
If the dead time feature is used, TI recommends placing the programming
resistor RDT and bypassing capacitor close to the DT pin of the UCC21530-Q1 to prevent noise from unintentionally coupling to
the internal dead time circuit. The capacitor should be
≤1
nF.