SLUSDG3F August 2018 – September 2024
PRODUCTION DATA
The recommended input supply voltage (VCCI) for UCC21530-Q1 is between 3 V and 18 V. The output bias supply voltage (VDDA/VDDB) range depends on which version of UCC21530-Q1 one is using. The lower end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information on UVLO see Section 7.3.1). The upper end of the VDDA/VDDB range depends on the maximum gate voltage of the power device being driven by UCC21530-Q1. All versions of UCC21530-Q1 have a recommended maximum VDDA/VDDB of 25 V.
Place a local bypass capacitor between the VDD and VSS pins. Position this capacitor as close to the device as possible. Use a low ESR, ceramic surface mount capacitor. Place two such capacitors: one with a value of between 220 nF and 10 µF for device biasing, and an additional 100-nF capacitor in parallel for high frequency filtering.
Similarly, place a bypass capacitor between the VCCI and GND pins. Given the small amount of current drawn by the logic circuitry within the input side of UCC21530-Q1, this bypass capacitor has a minimum recommended value of 100 nF.