SLUSDG3F August   2018  – September 2024

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings (Automotive)
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Enable Response Time
    4. 6.4 Programable Dead Time
    5. 6.5 Power-Up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in UCC21530-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 DT Pin Tied to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select Dead Time Resistor and Capacitor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Estimate Gate Driver Power Loss
        5. 8.2.2.5 Estimating Junction Temperature
        6. 8.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.6.1 Selecting a VCCI Capacitor
        7. 8.2.2.7 Other Application Example Circuits
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement Considerations
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

5.8 Electrical Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V (for 8V and 12V UVLO variants) or 20V (for 17V UVLO variant), 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCCI VCCI quiescent current VINA = 0 V, VINB = 0 V 1.4 2.0 mA
IVDDA, IVDDB VDDA and VDDB quiescent current VINA = 0 V, VINB = 0 V 1.0 2.5 mA
IVCCI VCCI operating current (f = 500 kHz) current per channel 3 3.5 mA
IVDDA, IVDDB VDDA and VDDB operating current (f = 500 kHz) current per channel, COUT = 100 pF 2.5 4.2 mA
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ON UVLO Rising threshold 2.55 2.7 2.85 V
VVCCI_OFF UVLO Falling threshold 2.35 2.5 2.65 V
VVCCI_HYS UVLO Threshold hysteresis 0.2 V
VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVDDA_ON, VVDDB_ON UVLO Rising threshold 8-V UVLO 7.7 8.5 8.9 V
VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 8-V UVLO 7.2 7.9 8.4 V
VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 8-V UVLO 0.6 V
VVDDA_ON, VVDDB_ON UVLO Rising threshold 12-V UVLO 11.7 12.5 13.3  V
VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 12-V UVLO 10.7 11.5 12.3 V
VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 12-V UVLO 1 V
VVDDA_ON, VVDDB_ON UVLO Rising threshold 17-V UVLO 16.4 17.6 18.8 V
VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 17-V UVLO 15.4 16.6 17.8 V
VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 17-V UVLO 1 V
INA, INB AND ENABLE
VINAH, VINBH, VENH Input high threshold voltage 1.2 1.8 2 V
VINAL, VINBL, VENL Input low threshold voltage 0.8 1 1.2 V
VINA_HYS, VINB_HYS, VEN_HYS Input threshold hysteresis 0.8 V
VINA, VINB Negative transient, ref to GND, 100 ns pulse Not production tested, bench test only –5 V
OUTPUT
IOA+, IOB+ Peak output source current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 4 A
IOA-, IOB- Peak output sink current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 6 A
ROHA, ROHB Output resistance at high state IOUT = –10 mA, TA = 25°C, ROHA, ROHB do not represent drive pull-up performance. See tRISE in Section 5.10 and Section 7.3.4 for details. 5 Ω
ROLA, ROLB Output resistance at low state IOUT = 10 mA, TA = 25°C 0.55 Ω
VOHA, VOHB Output voltage at high state VVDDA, VVDDB = 15 V, IOUT = –10 mA, TA = 25°C 14.95 V
VOLA, VOLB Output voltage at low state VVDDA, VVDDB = 15 V, IOUT = 10 mA, TA = 25°C 5.5 mV
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