米6体育平台手机版

SLUUBY1B December 2020 – April 2022 BQ76942

6.1 0x00 Control Status() and 0x12 Battery Status() Commands

The BQ76942 device includes 0x00 Control Status() and 0x12 Battery Status() commands, which report various status information on the pack. The 0x00 Control Status() command behaves similarly to 0x3E and 0x3F when written, this functionality is included for legacy auto-detection and is not recommended for customer usage. When this command is read back immediately after it has been written, it will return 0xFFA5 once. Subsequent reads will return the 0x00 Control Status() data, which is described below with the 0x12 Battery Status() details.

Table 6-1 0x00 Control Status() Bit Definitions

Bit	Name	Description
15 - 3	RSVD	Reserved
2	DEEPSLEEP	This bit indicates whether or not the device is in DEEPSLEEP mode. DEEPSLEEP = 0: Device is not in DEEPSLEEP mode. DEEPSLEEP = 1: Device is in DEEPSLEEP mode.
1	LD_TIMEOUT	This bit is set when the Load Detect function has timed out and checking has stopped. LD_TIMEOUT = 0: Load Detect function has not timed out or is inactive. LD_TIMEOUT = 1: Load Detection function timed out and was deactivated.
0	LD_ON	This bit indicates whether or not the Load Detect pullup was active during the previous LD pin voltage measurement. LD_ON = 0: LD pullup was not active during the previous LD pin measurement. LD_ON = 1: LD pullup was active during the previous LD pin measurement.

Table 6-2 0x12 Battery Status() Bit Definitions

Bit	Name	Description
15	SLEEP	This bit indicates whether or not the device is presently in SLEEP mode. SLEEP = 0: Device is not in SLEEP mode. SLEEP = 1: Device is in SLEEP mode.
14	RSVD	Reserved
13	SDM	SHUTDOWN mode is pending because the Shutdown() subcommand was received, or the RST_SHUT pin was asserted for > 1-sec. SDM = 0: Shutdown due to command or pin is not pending. SDM = 1: Shutdown due to command or pin is pending.
12	PF	Indicates whether a Permanent Fail fault has triggered. PF = 0: No Permanent Fail fault has triggered. PF = 1: At least one Permanent Fail fault has triggered.
11	SS	Indicates whether an enabled safety fault has triggered SS = 0: No safety fault is triggered. SS = 1: At least one enabled safety fault is triggered.
10	FUSE	Reports the most recently observed state of the FUSE pin, is updated every second in NORMAL mode. FUSE = 0: FUSE pin was not asserted by device or secondary protector at last sample. FUSE = 1: FUSE pin was asserted by device or secondary protector at last sample.
9	SEC1	SEC1:0 indicate the present security state of the device. SEC1:0 = 0: Device has not initialized yet. SEC1:0 = 1: Device is in FULLACCESS mode. SEC1:0 = 2: Device is in UNSEALED mode. SEC1:0 = 3: Device is in SEALED mode. When in SEALED mode, device configuration may not be read or written and some commands are restricted. When in UNSEALED mode, device configuration may normally be read and may be written while in CONFIG_UPDATE mode. When in FULLACCESS mode, unrestricted read and write access is allowed and all commands are accepted.
8	SEC0
7	OTPB	This bit indicates whether or not voltage and temperature conditions are valid for OTP programming. During normal operation, this bit will always be set if [[Manufacturing Status()[OTPW]]] is clear. When entering CONFIG_UPDATE mode, conditions will be checked and this bit will reflect whether or not programming is allowed ([[Manufacturing Status()[OTPW]]] does not apply in CONFIG_UPDATE mode). Once in CONFIG_UPDATE mode, this bit will not change state since no new measurements are being taken. OTPB = 0: OTP writes are allowed. OTPB = 1: Writes to OTP are blocked.
6	OTPW	This bit indicates whether or not some data is waiting to be written to OTP during normal operation. This can occur when, for example, configured to Permanent Fail information to OTP. This bit may remain set until conditions for OTP programming are met and all data is programmed. This bit is not set during OTP programming from CONFIG_UPDATE mode. OTPW = 0: No writes to OTP are pending. OTPW = 1: Writes to OTP are pending.
5	COW_CHK	This bit indicates while cell open-wire checks are occurring. When the feature is disabled, this bit will not set. When the feature is enabled, this bit will set periodically as the checks are performed. COW_CHK = 0: Device is not actively performing a cell open-wire check. COW_CHK = 1: Device is actively performing a cell open-wire check.
4	WD	This bit indicates whether or not the previous device reset was caused by the internal watchdog timer. This is not related to the Host Watchdog protection. WD = 0: Previous reset was normal. WD = 1: Previous reset was caused by the watchdog timer.
3	POR	This bit is set when the device fully resets. It is cleared upon exit of CONFIG_UPDATE mode. It can be used by the host to determine if any RAM configuration changes were lost due to a reset. POR = 0: Full reset has not occurred since last exit of CONFIG_UPDATE mode. POR = 1: Full reset has occurred since last exit of CONFIG_UPDATE and reconfiguration of any RAM settings is required.
2	SLEEP_EN	This bit indicates whether or not SLEEP mode is allowed based on configuration and commands. The [[Power Config[SLEEP_EN]]] bit sets the default state of this bit. The host may send commands to enable or disable SLEEP mode based on system requirements. When this bit is set, the device may transition to SLEEP mode when other SLEEP criteria are met. SLEEP_EN = 0: SLEEP mode is disabled by the host. SLEEP_EN = 1: SLEEP mode is allowed when other SLEEP conditions are met.
1	PCHG_MODE	This bit indicates whether or not the device is in PRECHARGE mode. In PRECHARGE mode, the PCHG FET is turned on instead of the CHG FET. PCHG_MODE = 0: Device is not in PRECHARGE mode. PCHG_MODE = 1: Device is in PRECHARGE mode.
0	CFGUPDATE	This bit indicates whether or not the device is in CONFIG_UPDATE mode. It will be set after the 0x0090 SET_CFGUPDATE() subcommand is received and fully processed. Configuration settings may be changed only while this bit is set. CFGUPDATE = 0: Device is not in CONFIG_UPDATE mode. CFGUPDATE = 1: Device is in CONFIG_UPDATE mode.