The BQ76942 device includes optional capability for the customer to calibrate each cell voltage gain and the gain for the stack voltage, the PACK pin voltage, and the LD pin voltage individually, and multifunction pin general ADC measurements. An offset calibration value Calibration:Vcell Offset:Vcell Offset is included for use with the cell voltage measurements, and Calibration:Vdiv Offset:Vdiv Offset is used with the TOS (stack), PACK, and LD voltage measurements. The cell voltage gains determined during calibration are written in Calibration:Voltage:Cell 1 Gain – Cell 10 Gain, where Cell 1 Gain is used for the measurement of VC1-VC0, Cell 2 Gain is used for the measurement of VC2-VC1, and so forth. Similarly, the calibration voltage gain for the TOS voltage should be written in Calibration:Voltage:TOS Gain, the PACK pin voltage gain in Calibration:Voltage:Pack Gain, the LD pin voltage gain in Calibration:Voltage:LD Gain, and multifunction pin general purpose ADCIN measurement gain in Calibration:Voltage:ADC Gain.

If values for the calibration gain configuration are not written, the BQ76942 device will use factory trim or default values for the respective gain values. When a calibration gain configuration value is written, the device will use that in place of any factory trim or default gain. The raw ADC measurement data (in units of counts) is corrected by first subtracting a stored offset trim value, then the gain is applied, then the Calibration:Vcell Offset:Vcell Offset (for cell voltage measurements) or the Calibration:Vdiv Offset:Vdiv Offset (for TOS, PACK, or LD voltage measurements) is subtracted, before the final voltage value is reported.

The factory trim values for the Cell Gain parameters can be read from the Cell Gain data memory registers while in FULLACCESS mode but not in CONFIG_UPDATE mode, if the data memory values have not been overwritten. While in CONFIG_UPDATE mode, the Cell Gain values will read back either with all zeros, if they have not been overwritten, or whatever values have been written to these registers. Upon exiting CONFIG_UPDATE mode, readback of the Cell Gain parameters will provide the values presently used in operation.

The cell voltage calibration can be implemented by applying two precise DC voltages to the cell input (such as 2.5 V and 4.5 V) and averaging multiple raw ADC measurements in 32-bit counts obtained from the 0x0071 - 0x0073 DASTATUS1–3() subcommands for each voltage. The gain can then be calculated as:

The offset for the cell voltage measurement can now be calculated as shown below:

The calibration for the TOS, PACK pin, and LD pin gain measurements can be implemented by similarly applying two precise DC voltages to the input and averaging multiple raw ADC measurements, which are provided in 16-bit counts from the 0xF081 READ_CAL1() subcommand. Note: one of the voltages can be skipped to reduce calibration time. The gain can then be calculated as:

The ADCIN measurement can be calibrated in similar fashion to the cell voltage gain calibration. One or two precise DC voltages can be applied to the selected pin, and the 32-bit counts obtained from the 0x0076 DASTATUS6() or 0x0077 DASTATUS7() subcommands for each voltage. The gain can then be calculated as:

The effective fullscale digital range of the cell measurement is 5 × VREF1, and the effective fullscale digital range of the ADCIN measurement is 1.667 × VREF1, although the voltages applied for these measurements should be limited based on the device electrical specifications. Using a value for VREF1 of 1.212 V, the nominal gain for the cell measurements is 12120, while the nominal gain for the ADCIN measurements is 4040. The reported voltages are calculated as: