The HDQ interface is an asynchronous return-to-one protocol where a processor communicates with the BQ76942 device using a single-wire connection to either the ALERT pin (Settings:Configuration:Comm Type = 3) or the HDQ pin (Settings:Configuration:Comm Type = 4). Note that the selected pin must be configured for use as the HDQ interface. Both the controller (host device) and responder (BQ76942) drive the HDQ interface using an open-drain driver, with a pullup resistor from the HDQ interface to a supply voltage required on the circuit board. The BQ76942 device can be changed from the default I²C communication mode to HDQ communication mode by sending the 0x7C40 SWAP_TO_HDQ() subcommand (at which point the device switches to HDQ mode using the ALERT pin immediately). Alternatively, the mode can be changed by setting the Settings:Configuration:Comm Type configuration register in CONFIG_UPDATE mode, then exiting CONFIG_UPDATE mode, then sending the 0x29BC SWAP_COMM_MODE() subcommand, at which point the device switches to the selected mode.

With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted first.

The 8-bit command code consists of two fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field (MSB Bit 7). The R/W field directs the device to do one of the following:

• Accept the next 8 bits as data from the host to the device, or
• Output 8 bits of data from the device to the host in response to the 7-bit command.

The HDQ peripheral on the BQ76942 device can transmit and receive data as an HDQ responder only.

The return-to-one data bit frame of HDQ consists of the following sections:

1. The first section is used to start the transmission by the host sending a Break (the host drives the HDQ interface to a logic-low state for a time t_(B)) followed by a Break Recovery (the host releases the HDQ interface for a time t_(BR)).
2. The next section is for host command transmission, where the host transmits 8 bits by driving the HDQ interface for 8 T_(CYCH) time slots. For each time slot, the HDQ line is driven low for a time T_(HW0) (host writing a "0") or T_(HW1) (host writing a "1"). The HDQ pin is then released and remains high to complete each T_(CYCH) time slot.
3. The next section is for data transmission where the host (if a write was initiated) or device (if a read was initiated) transmits 8 bits by driving the HDQ interface for 8 T_(CYCH) (if host is driving) or T_(CYCD) (if device is driving) time slots. The HDQ line is driven low for a time T_(HW0) (host writing a "0"), T_(HW1) (host writing a "1"), T_(DW0) (device writing a "0"), or T_(DW1) (device writing a "1"). The HDQ pin is then released and remains high to complete the time slot. The HDQ interface does not autoincrement, so a separate transaction must be sent for each byte to be transferred.