SLUUC72A September   2020  – October 2021 TPS542A50

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Before You Begin
  3. 2Description
    1. 2.1 Typical End-User Applications
    2. 2.2 EVM Features
    3. 2.3 TPS542A50EVM-059 PCB
  4. 3TPS542A50EVM-059 Bottom Circuit
    1. 3.1 Modifications
      1. 3.1.1 Output Voltage Setpoint
      2. 3.1.2 Enable and Undervoltage Lockout
      3. 3.1.3 Programming and External Clock Synchronization
      4. 3.1.4 Load Step with Function Generator
    2. 3.2 TPS542A50EVM-059 Bottom Circuit Schematic
    3. 3.3 Test Setup and Results
      1. 3.3.1  Input/Output Connections
      2. 3.3.2  Start Up Procedure
      3. 3.3.3  Electrical Performance Specifications and Results
      4. 3.3.4  Efficiency
      5. 3.3.5  Power Loss
      6. 3.3.6  Load Regulation
      7. 3.3.7  Transient Response
      8. 3.3.8  Loop Response
      9. 3.3.9  Output Voltage Ripple
      10. 3.3.10 Thermal Data
  5. 4TPS542A50EVM-059 Top Circuit (Small layout area design)
    1. 4.1 Modifications
      1. 4.1.1 Output Voltage Setpoint
      2. 4.1.2 Enable and Undervoltage Lockout
      3. 4.1.3 Programming and External Clock Synchronization
      4. 4.1.4 Load Step with Function Generator
    2. 4.2 TPS542A50EVM-059 Top Circuit (Small Layout Area) Schematic
    3. 4.3 Test Setup and Results
      1. 4.3.1  Input/Output Connections
      2. 4.3.2  Start Up Procedure
      3. 4.3.3  Electrical Performance Specifications and Results
      4. 4.3.4  Efficiency
      5. 4.3.5  Power Loss
      6. 4.3.6  Load Regulation
      7. 4.3.7  Line Regulation
      8. 4.3.8  Transient Response
      9. 4.3.9  Loop Response
      10. 4.3.10 Output Voltage Ripple
      11. 4.3.11 Start Up
  6. 5TPS542A50EVM-059 PCB Layout
  7. 6List of Materials
  8. 7Revision History

4.1.3 Programming and External Clock Synchronization

To enter programming mode, the SYNC pin (TP12_2) must be brought high while keeping the EN pin (J3_2-2 or TP14_2) low. The device is then programmed via the I2C pins (SCL and SDA). In this circuit, the SCL pin is connected to TP10_2, and the SDA pin is connected to TP11_2. After the device is enabled, all registers are read-only. Details on the valid I2C registers and instructions are provided in the TPS542A50 data sheet.

Note: This circuit does not have I2C pull-up resistors and must be provided by externally or by the I2C master device. The maximum recommended I2C pull-up voltage is 5.5 V.

An external signal (recommended 0-V to 3.3-V) can be used as an external clock synchronization source. To use this feature, the TPS542A50 must be enabled by bringing the EN pin (J3_2-2 or TP14_2) high, or leaving it floating. The external clock synchronization signal should be applied to the SYNC (TP12_2) pin, referenced to AGND. The external clock synchronization source must also be within -10% to +10% of the set switching frequency. This is true whether the switching frequency is selected using a resistor from FSEL to AGND (R6_2), or selected via I2C.
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