To operate the TPS92520EVM-133 with less than 40 V, then J11 must be
removed and the VBIAS test point (TP1) needs to be connected to VIN, assuming that
it is below 40 V, or can be connected to an external power supply.
Figure 6-2 Input Voltage Selection
Circuit Based on Operating Input Voltage
The TPS92520-Q1 can be setup with a resistor divider that
sets the UVLO rising and falling. See the TPS92520-Q1 data sheet for
additional information. Table 6-1 shows the
VUDIM rising and falling specifications from the data sheet. Always
check the data sheet to verify no changes have occurred since publication.
Table 6-1 UDIMx and UVLO Specifications
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
PWM DIMMING and
PROGRAMMABLE UVLO INPUT (UDIMx)
VUDIMx(EN)
UDIM input threshold sensed inductor current
ripple
Rising
1.22
1.27
V
Falling
1.075
1.120
V
The UVLO feature using a resistor divider on UDIM pins is described and outlined in the Figure 6-3 and Equation 1. See the data sheet for additional information.
Figure 6-3 TPS92520-Q1 Diagram for
UVLO Rising and Falling
Figure 6-4 TPS92520EVM-133 UVLO Rising Schematic and Calculations
If the UVLO rising and falling needs to be disabled, then connect UDIM1 (TP2) and UDIM2 (TP14) to
V5D. If the TPS92520EVM-133 is to be used below 40 V then see Figure 6-5.
Figure 6-5 Connections for Operating
the TPS92520EVM-133 at VINs Less Than 40 V and Having UVLO Disabled
Note that if UDIMx is attached to V5D, then only the internal PWM settings can
be used. The other option is to adjust UVLO rising by changing R4 for channel 1 and
R17 for channel 2 using the equation for VIN(RISE), which allows using
external PWM dimming, see Figure 6-6.
Figure 6-6 Bottom Side of TPS92510EVM-132 With UVLO Resistors of UDIM for Channel 1 and 2