SLUUCC4A October 2020 – September 2021 TPS92520-Q1
- Trademarks
- General Texas Instruments High Voltage Evaluation (TI HV EMV) User Safety Guidelines
- 1Description
- 2Performance Specifications
- 3Performance Data and Typical Characteristic Curves
- 4Schematic, PCB Layout, and Bill of Materials
- 5Software
- 6TPS92520EVM-133 Power Up and Operation
- 7Revision History
4.2 Layout
The TPS92520EVM-133 is a 4-layer board. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 illustrate the assembly, the top, the inner-layer1, the inner-layer2 and the bottom side of the TPS92520EVM-133 PCB layout. The Inner-layer 1 is a ground plane and there is no routing on this layer.
Figure 4-3 TPS92520EVM-133 Assembly Drawing
Figure 4-4 TPS92520EVM-133 Top Layer and Top Overlay (Top View)
Figure 4-5 TPS92520EVM-133 Inner-Layer 1
Figure 4-6 TPS92520EVM-133 Inner-Layer 2
Figure 4-7 TPS92520EVM-133 Bottom Layer and Bottom Overlay (Bottom View)