SLUUCF2C January 2021 – May 2022 BQ769142
Class | Subclass | Name | Type | Min | Max | Default | Unit |
---|---|---|---|---|---|---|---|
Settings | Protection | DSG FET Protections B | U1 | 0x00 | 0xFF | 0xE6 | Hex |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OTF | OTINT | OTD | RSVD_0 | RSVD_0 | UTINT | UTD | RSVD_0 |
Description: This bitfield configures which protections will disable the DSG FET. DSG FET action for any non-reserved bits may be individually selected.
Bit | Field | Default | Description |
---|---|---|---|
7 | OTF | 1 | FET Overtemperature 0 = DSG FET is not disabled when protection is triggered. 1 = DSG FET is disabled when protection is triggered. |
6 | OTINT | 1 | Internal Overtemperature 0 = DSG FET is not disabled when protection is triggered. 1 = DSG FET is disabled when protection is triggered. |
5 | OTD | 1 | Overtemperature in Discharge 0 = DSG FET is not disabled when protection is triggered. 1 = DSG FET is disabled when protection is triggered. |
2 | UTINT | 1 | Internal Undertemperature 0 = DSG FET is not disabled when protection is triggered. 1 = DSG FET is disabled when protection is triggered. |
1 | UTD | 1 | Undertemperature in Discharge 0 = DSG FET is not disabled when protection is triggered. 1 = DSG FET is disabled when protection is triggered. |