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SLUUCG7 April 2024 BQ76922

12.1 Direct Commands

Table 12-1 Direct Commands Table

Command	Name	Units	Type	Access	Description
0x00	Control Status	Hex	H2	Sealed: R/W Unsealed: R/W Full Access: R/W	When read, this command provides device status bits. This command behaves similarly to 0x3E/0x3F when written. When read back immediately after word write, it will return 0xFFA5 once. Subsequent reads will return Control Status. Writing this command is used for legacy auto-detection, and it is not recommended for customers to write to it. Bit descriptions can be found in Control Status Register.
0x02	Safety Alert A	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual alert signals when enabled safety alerts have triggered. Bit descriptions can be found in Safety Alert A Register.
0x03	Safety Status A	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual fault signals when enabled safety faults have triggered. Bit descriptions can be found in Safety Status A Register.
0x04	Safety Alert B	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual alert signals when enabled safety alerts have triggered. Bit descriptions can be found in Safety Alert B Register.
0x05	Safety Status B	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual fault signals when enabled safety faults have triggered. Bit descriptions can be found in Safety Status B Register.
0x06	Safety Alert C	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual alert signals when enabled safety alerts have triggered. Bit descriptions can be found in Safety Alert C Register.
0x07	Safety Status C	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual fault signals when enabled safety faults have triggered. Bit descriptions can be found in Safety Status C Register.
0x0A	PF Alert A	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual alert signals when enabled Permanent Fail alerts have triggered. Bit descriptions can be found in PF Alert A Register.
0x0B	PF Status A	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual fault signals when enabled Permanent Fail faults have triggered. Bit descriptions can be found in PF Status A Register.
0x0C	PF Alert B	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual alert signals when enabled Permanent Fail alerts have triggered. Bit descriptions can be found in PF Alert B Register.
0x0D	PF Status B	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual fault signals when enabled Permanent Fail faults have triggered. Bit descriptions can be found in PF Status B Register.
0x0E	PF Alert C	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual alert signals when enabled Permanent Fail alerts have triggered. Bit descriptions can be found in PF Alert C Register.
0x0F	PF Status C	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual fault signals when enabled Permanent Fail faults have triggered. Bit descriptions can be found in PF Status C Register.
0x10	PF Alert D	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual alert signals when enabled Permanent Fail alerts have triggered. Bit descriptions can be found in PF Alert D Register.
0x11	PF Status D	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides individual fault signals when enabled Permanent Fail faults have triggered. Bit descriptions can be found in PF Status D Register.
0x12	Battery Status	Hex	H2	Sealed: R Unsealed: R Full Access: R	Flags related to battery status Bit descriptions can be found in Battery Status Register.
0x14	Cell 1 Voltage	mV	I2	Sealed: R Unsealed: R Full Access: R	16-bit voltage on cell 1
0x16	Cell 2 Voltage	mV	I2	Sealed: R Unsealed: R Full Access: R	16-bit voltage on cell 2
0x18	Cell 3 Voltage	mV	I2	Sealed: R Unsealed: R Full Access: R	16-bit voltage on cell 3
0x1A	Cell 4 Voltage	mV	I2	Sealed: R Unsealed: R Full Access: R	16-bit voltage on cell 4
0x1C	Cell 5 Voltage	mV	I2	Sealed: R Unsealed: R Full Access: R	16-bit voltage on cell 5
0x34	Stack Voltage	userV	I2	Sealed: R Unsealed: R Full Access: R	16-bit voltage on top of stack
0x36	PACK Pin Voltage	userV	I2	Sealed: R Unsealed: R Full Access: R	16-bit voltage on PACK pin
0x38	LD Pin Voltage	userV	I2	Sealed: R Unsealed: R Full Access: R	16-bit voltage on LD pin
0x3A	CC2 Current	userA	I2	Sealed: R Unsealed: R Full Access: R	16-bit CC2 current
0x62	Alarm Status	Hex	H2	Sealed: R/W Unsealed: R/W Full Access: R/W	Latched signal used to assert the ALERT pin. Write a bit high to clear the latch. Bit descriptions can be found in Alarm Status Register.
0x64	Alarm Raw Status	Hex	H2	Sealed: R Unsealed: R Full Access: R	Unlatched value of flags which can be selected to be latched (using Alarm Enable()) and used to assert the ALERT pin. Bit descriptions can be found in Alarm Raw Status Register.
0x66	Alarm Enable	Hex	H2	Sealed: R/W Unsealed: R/W Full Access: R/W	Mask for Alarm Status(). Can be written to change during operation to change which alarm sources are enabled. The default value of this parameter is set by Settings:Alarm:Default Alarm Mask. Bit descriptions can be found in Alarm Enable Register.
0x68	Int Temperature	0.1 K	I2	Sealed: R Unsealed: R Full Access: R	This is the most recent measured internal die temperature.
0x6A	CFETOFF Temperature	0.1 K	I2	Sealed: R Unsealed: R Full Access: R	When the CFETOFF pin is configured as a thermistor input, this reports its most recent temperature measurement. When configured as ADCIN, this instead reports the measured voltage at the CFETOFF pin in millivolts.
0x6C	DFETOFF Temperature	0.1 K	I2	Sealed: R Unsealed: R Full Access: R	When the DFETOFF pin is configured as a thermistor input, this reports its most recent temperature measurement. When configured as ADCIN, this instead reports the measured voltage at the DFETOFF pin in millivolts.
0x6E	ALERT Temperature	0.1 K	I2	Sealed: R Unsealed: R Full Access: R	When the ALERT pin is configured as a thermistor input, this reports its most recent temperature measurement. When configured as ADCIN, this instead reports the measured voltage at the ALERT pin in millivolts.
0x70	TS1 Temperature	0.1 K	I2	Sealed: R Unsealed: R Full Access: R	When the TS1 pin is configured as a thermistor input, this reports its most recent temperature measurement. When configured as ADCIN, this instead reports the measured voltage at the TS1 pin in millivolts.
0x72	TS2 Temperature	0.1 K	I2	Sealed: R Unsealed: R Full Access: R	When the TS2 pin is configured as a thermistor input, this reports its most recent temperature measurement. When configured as ADCIN, this instead reports the measured voltage at the TS2 pin in millivolts.
0x7F	FET Status	Hex	H1	Sealed: R Unsealed: R Full Access: R	Provides flags showing status of FETs and ALERT pin. Bit descriptions can be found in FET Status Register.