The following images show the board layout for the TPS51383EVM and TPS51384EVM. The TPS51383EVM and TPS51384EVM have four layers. The top layer contains the main power traces for VIN, VOUT, and GND. Also on the top layer are connections for the pins of the TPS51383EVM and TPS51384EVM and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors, C3, C4, C5, and C6 are located as close to VIN pins and PGND pins of the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with signal ground copper fill and the feedback trace from the point of regulation to the top of the resistor divider network. Two inner layers are ground plane.